Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
Non-binary low-density parity-check codes have superior communications performance compared to their binary counterparts. However, to be an option for future standards, efficient hardware architectures must be developed. State-of-the-art decoding algorithms lead to architectures suffering from low throughput and high latency. The check node function accounts for the largest part of the decoders overall...
The added encoding efficiency and visual quality that is offered by the latest HEVC standard is mostly attained at the cost of a significant increase of the computational complexity at both the encoder and decoder. However, such added complexity greatly compromises the implementation of this standard in computational and energy constrained devices, including embedded systems, mobile and battery supplied...
This work addresses the reversible circuit design using novel modularization approach by presenting architecture of a logically reversible processor based on the Von Neumann architecture that can operate with very low power consumption, protection of power analysis attack and long span of life due to less heat dissipation. The organization and architecture of the proposed processor is designed from...
High Efficiency Video Coding (HEVC) is becoming more and more important in current consumer application platforms. Compared with H264 standard, it can reach up to 8192×4320 resolutions at 120fps. To accelerate HEVC decoding processing, this paper presents an efficient hardware entropy decoding architecture, Entropy decoding includes Colomb and CABAC decoding. Hierarchy ring buffer is designed to storage...
In this paper, we have implemented a dynamic pipeline-partitioning video decoder for the symmetric stream multiprocessor (SSMP) architecture. The SSMP architecture extends the traditional symmetric multiprocessor (SMP) architecture with dedicated per-core scratchpad memories and inter-processor communication (IPC) controllers for efficient data passing between the processor cores. The SSMP architecture...
Dynamic Binary Translation (DBT) allows software compiled for one Instruction Set Architecture (ISA) to be executed on a processor supporting a different ISA. Some modern DBT systems decouple their main execution loop from the built-in Just-In-Time (JIT) compiler, i.e. the JIT compiler can operate asynchronously in a different thread without blocking program execution. However, this creates a problem...
This paper presents a new row decoding architecture implemented in 90nm STM10 triple well CMOS technology for low supply voltage, high speed NOR type Flash memories. The overall design is complemented with a novel stress relaxed high/low or positive/negative level shifter for converting the digital signals operating at 1.2V to higher supply voltages for high voltage applications. The proposed level...
The emerging computational complexities arises the need of fast multiplication unit. The importance of multiplication in various applications necessitates improvement in its design so as to obtain the multiplication result efficiently. Multiplication operation can be improved by reducing the number of partial products to be added and by enhancing the adder unit for obtaining sum. The number of partial...
The emerging computational complexities arises the need of fast multiplication unit. The importance of multiplication in various applications necessitates improvement in its design so as to obtain the multiplication result efficiently. Multiplication operation can be improved by reducing the number of partial products to be added and by enhancing the adder unit for obtaining sum. The number of partial...
Floating point operations are important and essential part of many scientific and engineering applications. Floating point coprocessor (FPU) performs operations like addition, subtraction, division, square root, multiplication, fused multiply and accumulate and compare. Floating point operations are part of ARM, MIPS, and RISC-V etc. instruction sets. The FPU can be a part of hardware or be implemented...
This paper first proposes two new LDPC decoding algorithms that may be seen as imprecise versions of the Offset Min-Sum (OMS) decoding: the Partially OMS, which performs only partially the offset correction, and the Imprecise Partially OMS, which introduces a further level of impreciseness in the check-node processing unit. We show that they allow significant reduction in the memory (25% with respect...
A 4K and Main-10 HEVC video decoder LSI is fabricated in a 28nm CMOS process. It adopts a block-concealed processor (BcP) to improve the visual quality and a bandwidth-suppressed processor (BsP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. It features fully core scalable (FCS) architecture which lowers the required working frequency...
Polar codes are the first error-correcting codes to provably achieve the channel capacity but with infinite code-lengths. For finite codelengths the existing decoder architectures are limited in working frequency by the partial sums computation unit. We explain in this paper how the partial sums computation can be seen as a matrix multiplication. Then, an efficient hardware implementation of this...
Long term evolution (LTE)-advanced aims the peak data rates in excess of 3 Gbps for the next generation wireless communication systems. Turbo codes, the specified channel coding scheme in LTE, suffers from a low-decoding throughput due to its iterative decoding algorithm. One efficient approach to achieve a promising throughput is to use multiple Maximum a Posteriori (MAP) cores in parallel, resulting...
A 16 bit low power pipelined RISC processor is proposed by us in this paper, the RISC processor consists of the block mainly ALU, Universal shift register and Barrel Shifter. We have used modified Harvard architecture that uses separate memories for its instruction & data memory response where as in the other architecture by von Neumann, has only one shared memory for instruction and data, with...
This paper presents a hybrid multimode Bose Chaudhuri Hocquenghem (BCH) encoder for reducing the input length of Syndrome calculation (SC) based on re-encoding approach. In previous re-encoding approaches, a conventional BCH encoder with long generator polynomials is used as a remainder operator to reduce the input length of SC. However, the input length is still large since long polynomial is used...
Modern video compression algorithms put significant strain on a system's CPU, especially for video encoding. The ever increasing demands for using video compression algorithms in a wide range of applications necessitate the use of processing components that boost the speed and quality of the video compression algorithm's execution. The vast parallel computational capabilities of modern graphics processing...
We focus on the metric sorter unit of successive cancellation list decoders for polar codes, which lies on the critical path in all current hardware implementations of the decoder. We review existing metric sorter architectures and we propose two new architectures that exploit the structure of the path metrics in a log-likelihood ratio based formulation of successive cancellation list decoding. Our...
In this paper, we first reveal the similarity of polar encoder and fast Fourier transform (FFT) processor. Based on this, both feed-forward and feed-back pipelined implementations of polar encoder are proposed. It is pointed out that the feedback part of SC polar decoder is nothing but a simplified version of polar encoder and therefore can be pipelined implemented also. Moreover, a general approach...
Polar codes have emerged as the most favorable channel codes for their unique capacity-achieving property. To date, numerous approaches for efficient decoding of polar codes have been reported. However, these prior efforts focused on design of polar decoders via deterministic computation, while the behavior of stochastic polar decoder, which can have potential advantages such as low complexity and...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.