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This paper focuses Two's complement multipliers with Shortest Bit-size were used without any increase in the delay of the partial product stage. This was done by reducing one row the maximum height of the partial product array generated by a radix-4 Modified Booth multiplier, this reduction may allow for a faster compression of the partial product array and regular layout. By using this method, it...
This paper presents a low complexity Min-Sum algorithm for decoding irregular Low-Density Parity-Check (LDPC) codes. In the proposed algorithm, the significant improvement in the error correcting performance without enhancing the hardware complexity is achieved by employing adaptive and optimized normalization factors for both the extrinsic information and log-likelihood ratio data bits respectively...
This paper describes high performance implementation of DVB-S2 modem on the rad-hard manycore RC64 DSP. Multi-level simulation and development methodologies are described. Modem algorithms are specified, together with implementation details. Efficient parallel processing is enabled by the shared memory architecture, by PRAM-like task oriented programming and by dynamic allocation of tasks to cores...
High-resolution digital-to-analog converters commonly employ segmented architecture. Its application requires thermometric decoder designing. This design process for high resolutions can become a challenge due to decoder complexity. In this paper, common design techniques of a thermometric decoder are discussed in details. The rule to form output logic functions is introduced. The formulas to calculate...
To address the high level of dynamism and variability in modern streaming applications (e.g. video decoding) as well as the difficulties in programming heterogeneous MPSoCs, we propose a novel execution model based upon both dataflow and Kahn process networks. This paper presents the semantics and properties of this hierarchical and parametric model, called DKPN. Parameters are classified and it is...
To address the high level of dynamism and variability in modern streaming applications (e.g. video decoding) as well as the difficulties in programming heterogeneous MPSoCs, we propose a novel execution model based upon both dataflow and Kahn process networks. This paper presents the semantics and properties of this hierarchical and parametric model, called DKPN. Parameters are classified and it is...
Digital watermarking is act of hiding data within a digital image in order to resolve issues related to authentication and copyrights. Reversible watermarking is suitable in sensitive applications like medical images, as it can recover original image after extraction of the watermark. Many reversible watermark schemes have been proposed earlier but there are very few hardware implementations available...
In this paper, a novel attempt is made to design a reconfigurable coder system which can be reconfigured on-the-fly to work either as an encoder, or decoder, or both encoder and decoder depending on the user requirements. In order to build the proposed reconfigurable system, Convolutional encoder, Viterbi decoder, Golay encoder and Golay decoder are employed in different combinations for the proposed...
The adoption of HLS has been driven by the need to tackle growing verification costs in traditional RTL design flows. This paper presents an overview of design, optimization and verification using HLS. It also outlines some of the requirements for HLS design to fit into existing design and verification flows and ways in which such flows might be adapted as HLS is more widely deployed.
A multi-mode QC-LDPC decoder is proposed to satisfy the 802.11n/ac WiFi standard. With code-specific design, the overall performance of the decoder is enhanced while ensuring an on-the-fly reconfigurable ability. The proposed architecture has been synthesized using an FPGA for measurements. A state-of-art error rate and implementation complexity are reported. Meanwhile, the throughput has been increased...
In a timestamp-base packet scheduler, which is an important part of Quality of Service (QoS) enabled network systems, Tag Sorting is the most critical step. This paper presents a high throughput pipelined architecture for Tag Sorting targeting FPGA technology. Our implementation results on Xilinx Virtex II pro 50 chip have shown that our design can run at a maximum clock frequency of 216 MHz and process...
Scatter-gather direct memory access (DMA) transfers can be used to efficiently fetch graph memory data for onchip processing of graph applications. We present a hardware controlled graph DMA engine which can operate autonomously without the need for CPU interaction. Graph processing algorithms can asynchronously request graph data which is fetched from memory and streamed to the processing core. An...
With the rapid increase of the network bandwidth, to process high throughput regular expressions with hardware has become inevitable. This paper presents a novel NFA-based algorithm. In this paper, two theorems were proved and were used to prove the correctness of the algorithm. Our approach was based on three basic modules to construct NFA that can be easily reused in a FPGA or ASIC. The quantitative...
This paper proposes frame-by-frame speech recognition as a hardware decoder on Field Programmable Gate Arrays (FPGAs). As a first step for FPGA implementation, Voice Activity Detection (VAD) using second order autocorrelation and a speech recognition decoder using formant frequency distances were evaluated. The hardware decoding was then implemented on an FPGA emulator. The VAD and decoder were demonstrated...
The computation of the Log-Likelihood Ratio (LLR) at the channel output may impose great demand of memory and hardware area, especially for high-order modulations. This paper introduces a new approach for the approximation of the LLR in AWGN channels based on the splitting of the original constellation into smaller sectors. Each new sector has a less complex configuration in which it is possible to...
An algorithm for synchronization of a decoder of a RFID receiver has been proposed, implemented and evaluated, by experimental setup. The solution can be used for UHF RFID (e.g. ISO18000-6 and EPC gen 2) readers using FM0, bi-phase or differential Manchester decoding. Goal of the proposed solution is the improved decoding of the received data in the presence of noise (so by using less power or working...
When high performance is required, the needed hardware implementation of trigonometric functions becomes often problematic. This paper generalizes and improves a CAM based arctangent architecture that has shown an exclusive appropriateness for some critical applications compared to the Look up Table based solution, the polynomial and the rational approximations. For more illustration, detailed design...
Fifth generation (5G) wireless networks require massive connectivity with a large number of devices and ask for non-orthogonal multiple access which has been proposed as a paradigm shift of physical layer technologies. Among all the existing non-orthogonal technologies where the number of users can be larger than the spreading factor, recently proposed sparse code multiple access (SCMA) is shown to...
Motivated by the demand for energy-efficient communication solutions in the next generation cellular network, a mixed-ADC receiver architecture for massive multiple input multiple output (MIMO) systems is proposed, which differs from previous works in that herein one-bit analog-to-digital converters (ADCs) partially replace the conventionally assumed high-resolution ADCs. The information-theoretic...
Protecting data is a critical part of life in the modern world. The science of protecting data, known as cryptography, makes use of secret keys to encrypt data in a format that is not easily decipherable. However, most modern cryptography systems use passwords to perform user authentication. These passwords are a weak link in the security chain, and are a common point of attack on cryptography schemes...
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