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OpenCL is a high-level language that allows mixed hardware/software systems to be specified and compiled to run on heterogeneous parallel computing platforms. The hardware parallelism can take the form of multi-core central processing units (CPUs), massively parallel graphics processing units (GPUs), and, most recently, field-programmable gate array (FPGA) fabrics. OpenCL compilers for CPUs and GPUs...
In order to improve energy efficiency of computation-intensive workloads in Cloud Radio Access Network (C-RAN), virtualized hardware accelerators (HA) are proposed in this paper. In C-RAN architecture, the base stations (BS) are running in the virtual machines. Virtualization mechanism of HA makes each BS feel like owning a HA exclusively, but actually BSs sharing the HAs. To tackle the problem of...
Complex programmable logic device (CPLD) can be reconfigured to perform any desired application, the main theme of this paper was to reconfigure the CPLD which performs addition operation after detecting the given sequence for the choice of implementing security for the particular operation just like password protection. It mainly focused on designing an adder which performs its addition operation...
Polar codes have become one of the most attractive topics in coding theory community because of their provable capacity-achieving property. Belief propagation (BP) algorithm, as one o f the popular approaches for decoding polar codes, has unique advantage of high parallelism but suffers from high computation complexity, which translates to very large silicon area and high power consumption. This paper,...
This paper introduces a new theoretical framework, akin to the use of imprecise message storage in Low Density Parity Check (LDPC) decoders, which is seen as an enabler for cost-effective hardware designs. The proposed framework is the one of Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), and it is shown to provide a unified approach for several designs previously proposed in the literature...
LDPC decoders on faulty hardware have received increasing attention over the last few years, mainly motivated by reliability issues in emerging nanotechnologies. As a main result, it was shown that LDPC decoders are naturally robust to hardware faults. LDPC encoders on faulty hardware have received less attention, and they are expected to be less robust to hardware faults. In this work, we propose...
This paper presents an efficient hardware design approach for list successive cancellation (LSC) decoding of polar codes. By applying path-overlapping scheme, for LSC with list size l (l > 1), the l instances of successive cancellation (SC) decoder can be cut down to only one. This results in a dramatic reduction of the hardware complexity without any decoding performance loss. We also develop...
Polar codes are an exciting new class of error correcting codes that achieve the symmetric capacity of memoryless channels. Many decoding algorithms were developed and implemented, addressing various application requirements: from error-correction performance rivaling that of LDPC codes to very high throughput or low-complexity decoders. In this work, we review the state of the art in polar decoders...
Rise in bandwidth requirement for multimedia processing is forcing designers to use complex or wider buses in SOCs. Compression schemes using bit serial codes offer a low complexity encoding solution to such problems. However, their inherent sequential nature makes it challenging to achieve real time throughput at the decoder end. Conventionally, this problem is addressed by high frequency application...
Conventional bit-flipping (BF) algorithms spectacularly fail to handle punctured LDPC codes as they use hard decisions and, therefore, they cannot effectively cope with zero-reliability punctured symbols. However, BF techniques lead to low-cost high-speed decoders. This paper introduces a novel method that enables the use of BF-based iterative decoders for punctured LDPC codes. An erasure preprocessor...
This article presents a simple, less computational complexity method for constructing exponent matrix (3, K) having girth at least 8 of quasi-cyclic low-density parity-check (QC-LDPC) codes based on subtraction method. The construction of code deals with the generation of exponent matrix by three formulas. This method is flexible for any block-column length K. The simulations are shown in comparison...
This work presents a highly reliable and tamper-resistant design of Physical Unclonable Function (PUF) exploiting Resistive Random Access Memory (RRAM). The RRAM PUF properties such as uniqueness and reliability are experimentally measured on 1 kb Hfû2 based RRAM arrays. Firstly, our experimental results show that selection of the split reference and offset of the split sense amplifier (S/A) significantly...
Low Density Parity Check (LDPC) codes have been widely used in communications systems due to their high error correction capabilities. Recently these codes are also investigated for being exploited in high performance storage systems, especially when Non-Volatile Memory (NVM) technologies are used. The main drawback of using LDPC codes in storage systems with a high number of parallel channels is...
Non-binary low-density parity-check codes have superior communications performance compared to their binary counterparts. However, to be an option for future standards, efficient hardware architectures are mandatory. State-of-the-art decoding algorithms result in architectures suffering from low throughput and high latency. The check node function accounts for the largest part of the decoders overall...
Galois Field arithmetic forms the basis of Reed-Solomon erasure coding techniques to protect storage or communication systems from failures. Most recent implementations of Galois Field arithmetic rely on 128-bit vector instructions, such as Intel's Streaming SIMD Extensions, which allows us to perform fast Galois Field computations. However, these implementations are not optimized for multi-threaded...
Iterative decoding algorithms for low-density parity check (LDPC) codes have an inherent fault tolerance. In this paper, we exploit this robustness and optimize an LDPC decoder for high energy efficiency: we reduce energy consumption by opportunistically increasing error rates in decoder memories, while still achieving successful decoding in the final iteration. We develop a theory-guided unequal...
Polar codes, introduced by Arikan, achieves the capacity of symmetric channels with “low encoding and decoding complexity” for a large class of underlying channels. Recently, polar code has become the most favourable error correcting code in the viewpoint of information theory due to its property of channel achieving capacity. Although the fully parallel polar code based encoder architecture processes...
Soft decision decoding for Reed-Solomon codes has been proven to provide large coding gains in comparison to conventional hard decision decoding. Out of the numerous soft decoding algorithms, information set decoding has turned out to be an efficient approach, if coding gains larger than 0.5 dB are desired for the widely used RS(255,239) code. In this paper we investigate new hardware implementations...
Wake-up Radio receivers (WuRx) must be energy-efficient for their integration into Wireless Sensor Networks (WSNs). The most energy-hungry component is the address decoding hardware and it is generally powered by the node battery. In this paper, an addressing mechanism is proposed and the decoding process is explained in detail, on the contrary of previous works. This paper also shows the energy reduction...
This paper presents a hardware implementation of a reversible watermarking system that can insert invisible, semi-fragile watermark information into digital image in real time. A content dependent binary watermark is generated based on Discrete Cosine Transform (DCT) coefficients of a set of blocks (8×8) that are selected pseudo randomly on the basis of the key supplied. The binary watermark is then...
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