The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Operational Transconductance Amplifier (OTA) is an amplifier which uses the differential input voltages and generates the output current. Therefore, it can be called as a voltage controlled current source. OTA is an important building block in designing of continuous time analog filters. Existing trend in continuous scaling down of the transistor size and reduction in power supply have added to the...
A fully-integrated ultra-wideband power amplifier (PA) for multi-mode multi-band applications is designed and implemented in a standard 0.25 μm Ultra-CMOS Silicon-on-Sapphire (SOS) technology. The PA consists of two series stacked Cascode configuration to achieve high output power while maintaining stability. The PA utilizes stacked transistor switches at the input to extend the operation bandwidth...
A 130-GHz OOK transmitter has been developed based on a 65-nm CMOS technology in this work. The transmitter is composed of a 130-GHz fundamental oscillator and a switch-based OOK modulator. The oscillator is based on an LC cross-coupled differential pair with a tapered buffer, while the switch adopts a 3-stage shunt configuration. The on/off power ratio of the switch is over 20 dB, and the transmitter...
Nanoscale CMOS Silicon on Insulator (SOI) technology is a design environment suitable for integrated circuits and systems. Watt-level stacked power amplifiers (PAs) implemented in CMOS SOI technology operating from RF to mm-wave frequencies have been demonstrated. The challenge is to improve PA efficiencies to the level achieved by GaAs and GaN technologies. CMOS SOI technology also offers a unique...
Phase-locked loops (PLLs) are de-facto clock generators in analog, digital, RF, and embedded systems to generate a high frequency output clock from a low frequency reference clock. Modern systems-on-chip (SoCs) require many such PLLs that cater to multi-core processors, memories, IO interfaces and power management. A ring-oscillator-based analog charge-pump PLL offers a flexible and power-efficient...
High-speed signaling over package substrates is key to delivering the promise of 2.5D integration. Applications abound and include high-density memory interfaces, sub-division of large dies to increase yield and lower development time, sub-division of a die to achieve upward or downward scalability, or connecting to an off-chip SerDes or optics engine. Each of these in-package applications typically...
Increasing mobile data demands are pushing cellular network capacity. Massive MIMO base stations with large antenna arrays and smaller cell sizes demand higher integration in radio transceivers than what is available [1].
Multilevel modulation formats, such as PAM-4, have been introduced in recent years for next generation wireline communication systems for more efficient use of the available link bandwidth. High-speed ADCs with digital signal processing (DSP) can provide robust performance for such systems to compensate for the severe channel impairment as the data rate continues to increase.
Technology advancement has recently made it attractive to replace the flash quantizer (QTZ) in a multibit ΔΣ modulator by an asynchronous successive-approximation-register (ASAR) QTZ to improve the overall power efficiency [1]. However, limited by the SAR throughput, most works in this regime report only a small signal bandwidth. To achieve a wide bandwidth, a lower oversampling ratio (OSR) can be...
The successive-approximation-register (SAR) architecture is well-known for its high power efficiency in medium-resolution A/D conversions. Together with time interleaving, it can challenge the regime of flash ADCs in high-speed, low-resolution applications [1]. However, when considered for high-precision, low-speed sensor readout interfaces, SAR ADCs suffer from nonlinearity resulting from capacitor...
CMOS Hall sensors are widely used as magnetic sensors due to their linearity and ease of integration [1–3]. Being essentially n-well resistors, their resolution is determined by thermal noise and so decreases with bandwidth (Fig. 11.3.1), limiting their use in wide-band current-sensing applications, such as in switched-mode power supplies, electric motor control and short-circuit detection. In contrast,...
Digital transmitters (DTX) have gained interest in the past few years because of their potential to provide compact die area, better efficiency due to the switching nature of the power amplifier core, and scaling with CMOS technology [1–3]. Quadrature DTX architecture [1] is favored over polar [3] or outphasing [4] for wideband applications, such as WiFi, because of its ability to scale easily to...
Cross-coupled pairs are certainly among the most widely adopted fundamental circuits still in use today. This elegant device arrangement yields broadband positive feedback with high gain and low power, desirable features both in analog and digital applications [1]. Its small signal properties are consistently leveraged in oscillators, impedance negators and to boost gain of transconductors, while...
In this paper, we present a low power consumption and high gain low noise amplifier using transformer feedback to neutralize the gate-source and gate-drain overlap capacitance of a FET. It is a single-ended amplifier designed in 65nm CMOS technology for 60 GHz transceiver. This LNA achieves a simulated gain of 10.64 dB, noise figure of 3.10 dB at 60 GHz.
This paper presents shadow filter configuration implemented using operational transresistance amplifier (OTRA). In shadow filters an external amplifier is added in the feed back loop of the basic filter and by controlling the gain of this amplifier the characteristics of the resulting filter can be tuned. Depending upon the value of A the filter characteristics can be varied from very low to very...
An S band octave bandwidth bandpass filter with loss compensation in 0.13 μm CMOS is presented. The minimum inductor filter topology is employed which is suitable for lumped element CMOS filters at low GHz frequencies. This filter benefits from the minimum number of inductors which results in less loss, smaller size, and lower cost. To further improve the filter performance, single-ended negative...
Direct RF under sampling reception has been developed to reduce the size and the power consumption of the terrestrial wireless terminals. We applied this reception method to Ku-band very small aperture terminal (VSAT). In this paper, we develop a CMOS sample and hold (S/H) IC for Ka-band VSAT receiver. Since Ka-band VSAT requires higher RF frequency operation (19.4–20.2 GHz) and wider system bandwidth...
The immense work presented in this paper is a high frequency sinusoidal oscillator using positive second generation current controlled conveyor (CCCII+) with minimum passive components. CCCII is implemented using single Current Feedback Operational Amplifier (CFOA) and single Operational Trans-conductance Amplifier (OTA). The frequency (time period) of CCCII is tuned to a maximum of 4 MHz using external...
A two-stage mm-wave power amplifier (PA) is presented. Designed in a 65 nm CMOS process, the PA employs capacitive neutralization in each stage for increased differential isolation and gain. Baluns are used for single-ended input/output signal to balanced signal conversion, and the interstage matching consists of a 2:1 transformer. With a 1.2 V supply, at 67 GHz, measurements show a gain of 16.8 dB,...
An improved phase frequency detector (PFD) and a novel charge pump (CP) for phase locked loop (PLL) applications are presented. The mechanisms for widening the phase error detection range and eliminating the dead zone are applied in the proposed PFD. To maintain a fast locked performance and a stable loop bandwidth for multi-standard frequency synthesizer applications, a programmable structure and...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.