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The k-means clustering is one of the widely used algorithms in Data Mining and Machine Learning domains due to the simplicity, efficiency and scalability involved. The algorithm allocates N data-points or samples to k-clusters employing the minimum distances from respective cluster centroids. Distance calculation is intrinsically a computationally intensive task which is usually accelerated by using...
This paper presents initial results for a novel 128-antenna massive Multiple-Input, Multiple- Output (MIMO) testbed developed through Bristol Is Open in collaboration with National Instruments and Lund University. We believe that the results presented here validate the adoption of massive MIMO as a key enabling technology for 5G and pave the way for further pragmatic research by the massive MIMO community...
Advanced Encryption Standard is used to cipher data with the motive of secure transmission over a communication channel. In this paper some architectures for AES-128 implementation have been discussed. The basic AES core has been developed for encryption and decryption using Look-up Table and Composite Field Arithmetic. It describes the basic structure of AES in Electronic Codebook mode working on...
In the analysis of next-generation DNA sequencing data, Hidden Markov Models (HMMs) are used to perform variant calling between DNA sequences and a reference genome. The PairHMM model is solved by the Forward Algorithm, for which the performance and power efficiency can be increased tremendously using systolic arrays (SAs) in FPGAs. We model the performance characteristics of such SAs, and propose...
This paper presents a hardware architecture for the QR decomposition (QRD) of a complex-valued matrix based on Modified Gram-Schmidt (MGS) algorithm. A high throughput iterative-pipelined design is implemented, which achieves similar performance of a fully parallel-pipelined design, with a significant reduction in hardware usage. For a fixed-point Field Programmable Gate Array (FPGA) implementation...
The paper presents the design and implementation of a high speed digital Finite Impulse Response (FIR) filter using unfolding transformation technique. FIR Filter has widespread applications in signal processing such as image processing, biomedical signal processing, high speed communication systems, noise elimination and many more. The speed of FIR filter can be improved with high speed vedic multiplier...
In this paper we propose an efficient hardware architecture for computation of matrix inversion of positive definite matrices. The algorithm chosen is LDL decomposition followed directly by equation system solving using back substitution. The architecture combines a high throughput with an efficient utilization of its hardware units. We also report FPGA implementation results that show that the architecture...
Internet of things (IoT) is communication between smart objects and human. It finds enormous applications in the field of healthcare monitoring, information management system, agriculture, predicting the natural disaster etc. In all those applications of IoT, security plays a vital role. In this paper, a study on various encryption light weight techniques used for IoT was analyzed. Also the performance...
Algorithms for data encryption are one of the most important parts of modern communication systems. In this paper the results of hardware implementation of AES256 and TDES algorithms are presented. AES256 and TDES are implemented as an IP core with AXI interface because of constant growth of data transfer requirements in modern embedded systems, in order to improve their capability. Beside details...
This paper proposes a QC-LDPC partial parallel architecture that implements a hard decision message passing algorithm based on Gallager-B decoding. The proposed architecture uses an optimized variable node unit, with adaptive threshold, suitable for irregular LDPC codes. We present implementation results for WiMAX rate 1/2 code for FPGA technology. These indicate a cost reduction of 2.5x in logic,...
To satisfy more and more complicated requirements on information recording, processing, exchange etc. in newly developed intelligent satellites, a distributed storage system is designed based on SpaceWire network in satellite platform. In this distributed storage system, a SpaceWire router unit serving as the core device of star network connects several nodes, including onboard computers, namely,...
Availability of OpenCL for FPGAs has raised new questions about the efficiency of massive thread-level parallelism on FPGAs. The general trend is toward creating deep pipelining and in-order execution of many OpenCL threads across a shared data-path. While this can be a very effective approach for regular kernels, its efficiency significantly diminishes for irregular kernels with runtime-dependent...
Large-scale deep convolutional neural networks (CNNs) are widely used in machine learning applications. While CNNs involve huge complexity, VLSI (ASIC and FPGA) chips that deliver high-density integration of computational resources are regarded as a promising platform for CNN's implementation. At massive parallelism of computational units, however, the external memory bandwidth, which is constrained...
A new, highly pixelated, PET scanner dedicated to mouse imaging is being developed based on the LabPET II detector module. Each module includes four monolithic array of 4×8 avalanche photodiodes (APD) individually coupled to four 4×8 array of 1.12×1.12 mm2 scintillator pixels aimed at achieving submillimetric spatial resolution. A PCB routes the signals from four detector arrays to two 64-channel,...
The emerging applications is the dominant factor that drives the evolvement of computer technologies and architectures. Among the emerging applications these days, neural networks are the most attention-grabbing one. To unleash the benefits of neural network, the architecture optimization is a necessity. In this paper, the architecture requirements of neural network is first reviewed. Then based on...
The contribution of this paper is implementing a high throughput LDPC codec in FPGA for quantum key distribution (QKD) system. By software, the throughput of error correction in QKD system via LDPC codec could only reach 1.8Mbps, which is not satisfactory for high speed QKD systems. Thus, it is desirable that LDPC error correction is realized in FPGA to increase the throughput. LDPC codec is implemented...
FPGA, or Field Programmable Gate Array, has been widely used for several applications such as digital signal and image processing, video processing, software-defined radio, radar processing, medical imaging and so on. Currently, with the significance growth of parallel computing and cloud computing application, FPGA provides another solution for high performance computing instead of CPU or GPGPU due...
This paper uses the Altera SDK for OpenCL (AOCL) High-Level Synthesis (HLS) tool to accelerate the computation of the SHA-1 hash function. Using FPGAs to increase throughput of this algorithm has been a popular topic in research. The work done thus far, focuses on HDL based design methodologies. The goal of this paper is to determine if the HLS implementation can compare in terms of speed to the HDL...
The image processing applications require low power and high speed, the convolution based 1D-DWT is not desirable. In this proposed architecture the modified 5/3 lifting algorithm is realized on FPGA platform with optimizations. The latency and throughput is optimized with the modified algorithm. The architecture is modelled using HDL and implemented on FPGA. The proposal operates at 178MHz and realised...
Hadoop is an emerging data application for the big data processing. In Hadoop system, data compression is a significant part in processing big data effectively. Achieving this in software requires significant compute processing. In this paper we present the detailed design of a hardware compression accelerators. We also measure the performance of the hardware accelerators. Our analysis shows that...
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