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Internet of things (IoT) is communication between smart objects and human. It finds enormous applications in the field of healthcare monitoring, information management system, agriculture, predicting the natural disaster etc. In all those applications of IoT, security plays a vital role. In this paper, a study on various encryption light weight techniques used for IoT was analyzed. Also the performance...
Algorithms for data encryption are one of the most important parts of modern communication systems. In this paper the results of hardware implementation of AES256 and TDES algorithms are presented. AES256 and TDES are implemented as an IP core with AXI interface because of constant growth of data transfer requirements in modern embedded systems, in order to improve their capability. Beside details...
Recent research has established that hardware overprovisioning can improve system power utilization as well as job throughput in power-constrained, high-performance computing environments significantly. These benefits, however, may be associated with an additional infrastructure cost, making hardware overprovisioned systems less viable economically. It is thus important to conduct a detailed cost-benefit...
Power is quickly becoming a first class resource management concern in HPC. Upcoming HPC systems will likely be hardware over-provisioned, which will require enhanced power management subsystems to prevent service interruption. To advance the state of the art in HPC power management research, we are implementing SLURM plugins to explore a range of power-aware scheduling strategies. Our goal is to...
Load balanced Birkhoff-von Neumann (BvN) switches are very popular due to low hardware complexity and high performance. But, for some traffic scenarios, the achieved throughput can be severely decreased. We propose a novel load balanced BvN based switch that is non-blocking (achieves 100% throughput) for any admissible traffic scenario. The proposed switch implements only one switch stage because...
SDN efficiency is driven by the ability of controllers to process small packets based on a global view of the network. The goal of such controllers is thus to treat new flows coming from hundreds of switches in a timely fashion. In this paper, we show this ideal remains impossible through the most extensive evaluation of SDN controllers. We evaluated five state-of-the-art SDN controllers and discovered...
With the recent roll-out of 100 Gbit Ethernet technology for high-performance computing applications and the technology for 100 Gbit wireless communication emerging on the horizon, it is just a matter of time until non-high performance computing applications will have to utilize these data rates. Since 10 Gbit/s protocol processing is already challenging for current server machines and simply upscaling...
The development of network services makes their requirements for bandwidth become higher and more various, which leads to difficulty in Quality of Service (QoS) guarantee. In this paper, an OpenFlow switch featuring Weighted Fair Queuing (WFQ) algorithm is proposed. The system is implemented into NetFPGA 1G board which utilizes Xilinx Virtex II Pro 50 technology. The results have shown that our circuit...
Of late an increasing amount of functionalityin computer networks is provided by commodityx86 hardware wherein the CPU is the main bottleneck. Relieving the CPU from a portion of its computationalstress leads to a lowered number of cycles spent on eachsingle packet. Subsequently, servers are able to dealwith millions of packets per second. We show a casestudy in which we used the cryptographic offloadingfunctionality...
In this paper, we consider a decoded-and-forward (DF) energy-harvesting system with multiple antennas in the presence of transmit hardware impairments. The relays are energy-constrained nodes that collect energy from the source signals using time-switching architecture. Two partial relay selection (PRS) schemes that are PRS-1 and PRS-2 are employed for simplifying the relay-selection complexity. In...
Availability of OpenCL for FPGAs has raised new questions about the efficiency of massive thread-level parallelism on FPGAs. The general trend is toward creating deep pipelining and in-order execution of many OpenCL threads across a shared data-path. While this can be a very effective approach for regular kernels, its efficiency significantly diminishes for irregular kernels with runtime-dependent...
Middleboxes, which implement specific network service functions – e.g. firewalls, load balancers, NATs – have traditionally been deployed as hardware appliances, thereby imposing significant constraints on network operators, who must ensure that the traffic is effectively routed to the appropriate set of middleboxes, following the right order. Being hardware-based, these boxes offer limited upgrade...
Irregularity is a recognized problem on many- and multi-core platforms but its effect remains to be studied. This paper focuses on multicore processors and assumes that packet traffic is processed by a large number of parallel jobs in realtime, while each job is implemented as a streaming algorithm. Analysis is performed using a real-life measurement dataset collected especially for this study while...
To achieve high throughput, core count in compute accelerators such as General-Purpose Graphics Processing Units (GPGPUs) increases continuously. The communication demand of these cores boosts the demand for a low-latency packet switched network. As packet latency is mainly composed of per-hop latency, contention latency and serialization latency, a favorable Network-on-Chip (NoC) design should efficiently...
With the data growth related to the increase of devices with network access, the high speed Ethernet is widely used in various fields from big data center to high frequency transaction (HFT). However, the conventional software-based protocol stack consumes large amount of CPU time at full transmission rate, and leads to low performance such as high latency and low throughput. This paper presents a...
In this paper, a novel design of Multi-Path Delay Commutator Architecture FFT processor(MDC-FFT) is proposed based on customized rotation factor ROM(RF-ROM) with various memory access mechanism for OFDM systems. For the OFDM systems, the combined FFT algorithm of Radix-2 FFT and Radix-22FFT is conducted. The pipeline architecture is also proposed for its high throughput and scalability. With hybrid...
High Efficiency Video Coding (HEVC) standard uses Discrete Cosine Transform (DCT) to compress energy. The minimum and the maximum Transform Unit (TU) size used in HEVC is 4 × 4 and 32 × 32, respectively. With large TU size coding efficiency improves. But, it is at the cost of increased hardware complexity. Further, achieving full hardware utilization and constant throughput is a challenging task....
High-Efficiency Video Coding (HEVC) is the current video coding technique proposed by MPEG and ITU jointly. HEVC uses variable size Discrete Cosine Transform (DCT) for spatial redundancy and this paper presents a high throughput DCT architecture for the same. Reconfigured Multiple Constant Multiplication (RMCM) technique is introduced in this paper to realize constants used in the DCT operation. Throughput...
This paper uses the Altera SDK for OpenCL (AOCL) High-Level Synthesis (HLS) tool to accelerate the computation of the SHA-1 hash function. Using FPGAs to increase throughput of this algorithm has been a popular topic in research. The work done thus far, focuses on HDL based design methodologies. The goal of this paper is to determine if the HLS implementation can compare in terms of speed to the HDL...
This paper presents an analysis performance of running multimedia applications on IPv4 compared to IPv6. As acknowledged, today's network faces anexhaustion of IPv4 addresses by Internet Assigned Numbers Authority (IANA) due to larger users need internet communication. Thus, migration from IPv4 to IPv6 is the main reason where some applications should be tested on its running performance on IPv6....
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