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Containers have been used in many applications for isolation purposes due to the lightweight, scalable and highly portable properties. However, to apply containers in virtual network functions (VNFs) faces a big challenge because high-performance VNFs often generate frequent communication workloads among containers while the container communications are generally not efficient. Compared with hardware...
Software-Defined Networking (SDN) is a framework conceived to make network infrastructures more programmable and more easily manageable. We explore the integration of the latter in Wireless Mesh Networks (WMNs) through the design of an opportunistic and self-configurable SDN solution. Opportunistic to be able to cope with the intermittent connectivity and network partitioning and merging scenarios...
Network Function Virtualization (NFV) brings agility and flexibility delivering network services with cost efficiency to network operators. As an emerging technology, it also presents several challenges, among them, ensuring high performance for virtualized network functions, based on software implementation and running on standard IT servers, instead of custom hardware appliances. In this article,...
In this paper, we present our view of massively-parallel heterogeneous computing for solving large scientific problems. We start by observing that computing has been the primary driver of major innovations since the beginning of the 21st century. We argue that this is the fruit of decades of progress in computing methods, technology, and systems. A high-level analysis on out-scaling and up-scaling...
The lower layer characteristics of 60 GHz wireless networks impact the entire protocol stack. This includes effects such as sudden link failure due to blockage, high packet loss due to deafness, or suboptimal transmit rates due to antenna misalignment. To understand the resulting behaviors at the upper layers, it is key to have access to lower layer information. At the time of writing, 60 GHz experimentation...
Scaling web applications such as e-commerce in cloud by adding or removing servers in the system is an important practice to handle workload variations, with the goal of achieving both high quality of service (QoS) and high resource efficiency. Through extensive scaling experiments of an n-tier application benchmark (RUBBoS), we have observed that scaling only hardware resources without appropriate...
This paper constructs a competiveness evaluation system of port with resource competitiveness, structure competitiveness, and transformation and upgrading competitiveness, from which we can learn core competitiveness of each port area specifically. Matter-element model is used to evaluate their competitiveness, through which we can not only figure out the competitiveness, but also trace back to the...
Virtualized datacenter networks have been deployed in production platforms, e.g., Amazon VPC and VMware's NVP, to offer the flexibility of network management to enterprise-level clients. A common characteristic of these platforms is that they adopt software switches, such as Open vSwitch (OvS), instead of hardware switches to transfer data between VMs. Although group communication is common in enterprise...
Recent studies have experimentally shown the gains of full-duplex radios. However, due to its relatively higher cost and complexity, we can envision a more practical step in the network evolution is to have a full-duplex access point (AP) but keep the clients half-duplex. Unfortunately, the full-duplex gains can hardly be extracted in practice as the uplink transmission from a half-duplex client introduces...
One step required several times for current video encoders is the residual coding loop, composed of the direct transformation, direct quantization, inverse quantization, and inverse transformation. These operations demand high throughput and low latency since their outputs must be processed by other steps of the coder. This paper proposes a high-throughput parallel and multiplierless hardware architecture...
Text analytics has become increasingly important in the past few years because of the substantial growth in the amount of research, business, and government needs. An efficient text analytics system is likely to require high-powered regular expression matching (REGEX), as REGEX operations dominate the whole execution time. Some approaches have exploited the parallelism of graphic processing units...
Reconfigurability of Field Programmable Gate Array (FPGA) makes it one of the most promising approaches in the implementation of the Software Defined Radio (SDR). FPGA Dynamic Partial Reconfiguration (DPR) feature emphasizes that approach by allowing the implemented SDR system to switch between multiple communications standards in runtime reusing the same FPGA hardware resources. Reconfiguration time...
Scheduling is a decision-making process that deals with the assignment of resources to tasks over given periods, aiming to optimize one or more objectives. Responsible for efficient distribution of the CPU time among the processes, scheduler has become an essential part of computer systems. While applications run on neighboring cores of a many-core system, they compete with each other for the shared...
The Internet of Things (IoT) constrained devices show the urgent need for low power data security hardware cores. This paper presents a power efficient AES Core fabricated in UMC 130 nm CMOS technology by using Faraday standard cells library. The maximum throughput of the proposed AES Core is up to 2.6 Gb/s consuming about 0.2148 mW/MHz at 1.2V. The Dynamic Voltage and Frequency Scaling (DVFS) technique...
Cipher-based message authentication code, CMAC, is a NIST approved standard for checking message integrity and authentication. This work presents a low-latency AES architecture for CMAC. The architecture uses intensive parallel processing per round and takes advantage of the BRAM present in modern FPGA. Experimental results show that for typical IoT application, the proposed architecture has a latency...
Many models of spiking neural networks heavily rely on exponential waveforms. On neuromorphic multiprocessor systems like SpiNNaker, they have to be approximated by dedicated algorithms, often dominating the processing load. Here we present a processor extension for fast calculation of exponentials, aimed at integration in the next-generation SpiNNaker system. Our implementation achieves single-LSB...
Due to the expensive hardware and complex management of the traditional middlebox, a concerted effort towards the virtualized middlebox has been launched in both academia and industry. In this paper, we propose a unified middlebox model, MBBrick, which is composed of three operation modules (classifier, rewriter, forwarder) and a control module (the mcontroller). We then design a language, MG, to...
Millimeter wave (mm-wave) communication is a topic of intensive recent study, as it allows to significantly boost data rates of future 5G networks. In this paper, we focus on a mm-wave system consisting of a single Access Point (AP) and two User Equipments (UEs), where one UE requires high throughput, while the other is characterized by a low latency demand. Given that setup, we aim at optimally allocating...
Designing a cost-effective network for data centers that can deliver sufficient bandwidth and provide high availability has drawn tremendous attentions recently. In this paper, we propose a novel server-centric network structure called RCube, which is energy efficient and can deploy a redundancy scheme to improve the availability of data centers. Moreover, RCube shares many good properties with BCube,...
IPsec is a suite of protocols that adds security to communications at the IP level. However, the high computing power required by the IPsec algorithms limits network connection performance. The paper presents the hardware implementation of IPsec gateway in FPGA. Efficiency of the proposed solution allows to use it in networks with data rates of several Gbit/s.
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