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The advent of 8K and better resolutions of video pose problems for the capture and storage of data by these standards. The contemporary alternative is to compromise on quality and use various (often lossy) compression techniques to reduce the bandwidth required to move this data. This paper proposes a novel method for handling large volumes of video data without compromising its quality through space...
The data transfer in the Grid at CERN (the European Organization for Nuclear Research) has seen constant improvement, be it through optimizing the existing tools, GridFTP and GFAL2 or by adding new tools such as XRootd. Unfortunately, all these have reached the maximum limit in terms of throughput. They are limited not by the network infrastructure, but by the fact that they use a single source for...
Increasingly, the application providers are using a separate fault management system that offers out-of-the-box monitoring and alarms support for application instances. A fault management system is usually distributed in nature and consists of a set of management components that does both fault detection and can trigger actions, for example, automatic restart of monitored components. Such a distributed...
Because of their performance characteristics, highperformance fabrics like Infiniband or OmniPath are interesting technologies for many local area network applications, including data acquisition systems for high-energy physics experiments like the ATLAS experiment at CERN. This paper analyzes existing APIs for high-performance fabrics and evaluates their suitability for data acquisition systems in...
Viterbi detectors are widely used in data recording channels in the timing loop as well as in the digital back end before error-correction decoding to detect data in the presence of inter-symbol interference (ISI) and noise. Further, soft reliability values assist in the decoding of outer codes. The state-of-the-art implementations of the Viterbi algorithm are synchronous which consider the ‘worst-case’...
In this paper, an FPGA-based implementation of Frequent Items Counting is proposed. The architecture deploys the equality comparator matrix for comparing the input items with themselves to count them instantly within a single operating clock. The proposed architecture is applied to the case of the 8-bit item. That means 256 different types of items in total. The system is built and verified on the...
The need for efficient Finite Impulse Response (FIR) filters in high-speed applications targets Field Programmable Gate Arrays (FPGAs) as an effective and flexible platform for digital implementation. Although FIR filter offer advantages like linear phase characteristic, no feedback loops and good system stability, its convolution nature poises a challenge in parallelization due to data dependency...
Convolutional encoder is widely applied in lots of wireless communication standards including 3G/4G mobile communications, DVB (Digital Video Broadcasting), IoT(Internet of Things) transmissions and so on. Therefore multi-standard Viterbi decoder design for the above receivers is a hot issue. In this paper, a reconfigurable high performance Viterbi decoder design is proposed for LTE, WiMAX, CDMA2000,...
In this paper, we push the limits in maximizing the throughput of side-channel-protected AES-GCM implementations on an FPGA. We present a fully unrolled and pipelined architecture that uses a Boolean masking countermeasure (specifically, threshold implementation) for first-order DPA resistance. Using a high-end Virtex-7 device, we obtain a throughput of 15.24 Gbit/s. Since masked implementations require...
This paper conducts a performance analysis of two popular private blockchain platforms, Hyperledger Fabric and Ethereum (private deployment), to assess the performance and limitations of these state-of-the-art platforms. Blockchain, a decentralized transaction and data management technology, is said to be the technology that will have similar impacts as the Internet had on people's lives. Many industries...
Using a new input restructuring sequence and an appropriate reordering of the elements involved, a new VLSI algorithm that uses short length pseudo-cycle convolution structures for the VLSI implementation of discrete sine transform is presented. It uses a new parallel decomposition of discrete sine transform (DST) that leads to a high throughput VLSI implementation with a low hardware cost. The proposed...
SDN controller platforms have supported clustering architecture to meet high scalability and availability requirements for large scale carrier grade networks. As a well-known open source project, OpenDaylight provides a clustering and distributed datastore architecture. Datastore is distributed into shards such that a subset of shard can be located in any cluster member. To guarantee strong consistency...
Today's data center servers are equipped with high speed and complex network adaptors, featuring an array of functions, e.g. hardware TX/RX queues, packet filters, rate limiters, etc. Recent work like IX, Arrakis, MultiStack has made us rekindle the user-level network stacks' innovation utilizing these commodity network adaptors. In this paper, we revisit the idea to move stacks' design from in-kernel...
This paper presents a fully pipelined layered decoder architecture for IEEE 802.11 n/ac/ax LDPC codes, free of idle cycles. Several decoder architectures for such codes have emerged in the literature featuring throughputs in the multi- Gbps range. The proposed architecture surpasses the highest reported throughput for IEEE 802.11 n/ac/ax LDPC codes. This is achieved 1) algorithmically, by implementing...
Field Programmable Gate Arrays (FPGAs) excel at the implementation of local operators in terms of throughput per energy since the off-chip communication can be reduced with an application-specific on-chip memory configuration. Furthermore, data-level parallelism can efficiently be exploited through socalled loop coarsening, which processes multiple horizontal pixels simultaneously. Moreover, existing...
Programmable Logic Controllers (PLCs) are specialized computing systems for the control and monitoring of distributed industrial devices. Aiming for a highly connected industrial Internet-of-Things (IoT) ecosystem, PLCopen OPC Unified Architecture (UA) specification has been released. This paper presents the implementation and evaluation of a PLCopen OPC-UA software component for industrial control...
In 5G heterogeneous evolution, the unlicensed band has captured much attention. Specified by 3GPP Release 13, LTE WLAN aggregation (LWA) is deemed as an effective approach for spectrum integration of 5G heterogeneous networks (HetNet). However, most of previous works about LWA lie in the architecture design, and rarely investigate LWA algorithm analytically. In this paper, we formulate the network...
Due to the rapid increase in data traffic, one of the solutions provided by mobile operators is to operate Long Term Evolution (LTE) in the unlicensed 5GHz band, as the licensed spectrum is becoming scarce. Mobile operators can expand their network capacity by operating LTE in the unlicensed band at lower cost when compared with using other licensed bands. Device to Device (D2D) communication, proven...
In this paper we present a complete, open-source GZIP compressor implementation for FPGA based on a systolic array architecture. GZIP is one of the most utilized compression algorithms. Besides the usual use-case of compression for data storage, distributed computing systems such as Hadoop utilize compression to reduce the amount of data which is transferred between computing nodes in a cluster. However,...
Interleave division multiple access (IDMA) is a potential candidate for the future fifth generation (5G) systems. In this paper, we propose a novel architecture for IDMA system with low latency while maintaining low complexity. In the conventional architecture, the IDMA receiver sequentially processes deinterleaving, despreading, spreading and interleaving for multiuser detection. The proposed architecture,...
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