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State-of-the-art channel coding schemes promise data rates close to the wireless channel capacity. However, efficient link adaptation techniques are required in order to deliver such throughputs in practice. Traditional rate adaptation schemes, which are reactive and try to “predict” the transmission mode that maximizes throughput based on “transmission quality indicators”, can be highly inefficient...
We present a new reliability-based hybrid automatic repeat request (RB-HARQ) scheme based on low density parity check (LDPC) codes. With the proposed RB-HARQ, which uses a rate-compatible LDPC code with puncturing and extending, the longest codeword is divided into clusters of code bits. Unlike previous works, in the event of a decoding failure, the receiver measures the reliability of received clusters,...
High-speed and low-area decoders for low-density parity-check (LDPC) codes with very long block lengths are challenging to implement due to the large amount of nodes and edges required. In this paper we implement a decoder for a (32643, 30592) LDPC code that has variable nodes of degree 7, check nodes degrees of 111 and 112, and 228501 edges, making fully-parallel hardware implementation unfeasible...
The recently proposed Glossy protocol demonstrated the high potential of constructive interference (CI) in improving communication performance in wireless sensor networks. This paper presents a network flooding protocol, Ripple, which also exploits CI while improving Glossy in terms of throughput and energy efficiency by a factor of three each. To this end, we propose to pipeline transmissions on...
This paper presents a high-throughput structured low density parity check (LDPC) code and an optimal parallel decoder architecture with advanced Ping-Pong RAMs for the HINOC 2.0 systems. An additional iteration scheme is proposed to further improve decoding performance by taking full use of time intervals of the discontinuous streams, an important feature in HINOC 2.0 systems. The proposed LDPC code...
This paper focuses on the beneficial effects brought by the presence of multiple receivers to a slotted Aloha scheme. Starting from an analytical angle, we review and compare some recent results that characterize the throughput of such systems under different channel models, based on the assumption that incoming powers at receivers follow an i.i.d. distribution. While practical in some scenarios,...
This paper first proposes two new LDPC decoding algorithms that may be seen as imprecise versions of the Offset Min-Sum (OMS) decoding: the Partially OMS, which performs only partially the offset correction, and the Imprecise Partially OMS, which introduces a further level of impreciseness in the check-node processing unit. We show that they allow significant reduction in the memory (25% with respect...
Network coding tends to increase not only the end-to-end delay due to unavoidable buffering of packets, but it also increases the inter-packet delay variations (jitter) due to batching. While an increase in delay does not necessarily adversely affect throughput, sudden delay spikes may interfere with TCP’s congestion avoidance mechanism. Such spikes are a common phenomenon in coded packet networks...
ALOHA-type protocols became a popular solution for distributed and uncoordinated multiple random access in wireless networks. However, such distributed operation of the Medium Access Control (MAC) layer leads to sub-optimal utilization of the shared channel. One of the reasons is the occurrence of collisions when more than one packet is transmitted at the same time. These packets cannot be decoded...
We consider a communication system with energy harvesting at a receiver for which the processing energy is the bottleneck. We propose using hybrid automatic retransmission request (HARQ) with soft combining to reduce the processing energy and improve the throughput under limited receiver energy. In this protocol, the receiver keeps requesting additional redundancy in order to increase the gap between...
Long term evolution (LTE)-advanced aims the peak data rates in excess of 3 Gbps for the next generation wireless communication systems. Turbo codes, the specified channel coding scheme in LTE, suffers from a low-decoding throughput due to its iterative decoding algorithm. One efficient approach to achieve a promising throughput is to use multiple Maximum a Posteriori (MAP) cores in parallel, resulting...
This paper presents a hybrid automatic repeat request (HARQ) scheme based on turbo product codes (TPC) error correction and self-detection. The TPC inherent error detection is used as an alternative to the conventional cyclic redundancy check (CRC) process and is utilized to implement partial retransmission. The proposed HARQ system attempts to identify the location of errors within the TPC codeword...
In this paper, we study the impact of a full-duplex secondary node on a cognitive cooperative network with Multipacket Reception (MPR) capabilities at the receivers. Motivated by recent schemes that make full-duplex communication feasible, we study a model with one primary and one secondary transmitter-receiver pair, where the secondary transmitter is able to relay primary unsuccessful packets. Cooperation...
This paper presents an energy-efficient VLSI implementation of Sparse Distributed Memory (SDM). High throughput and energy-efficient Hamming distance-based address decoder (CM-DEC) is proposed by employing compute memory [1], where computation is deeply embedded into a memory (SRAM). Hierarchical binary decision (HBD) is also proposed to enhance area- and energy-efficiency of read operation by minimizing...
A high-speed non-binary LDPC decoder based on Trellis Min-Max algorithm with layered schedule is presented. The proposed approach compresses the check-node output messages into a reduced set, decreasing the number of messages sent to the variable node. Additionally, the memory resources from the layered architecture are reduced. The proposed decoder was implemented for the (2304,2048) NB-LDPC code...
This work proposes an integrated remote terminal and bus controller: MIL-STD-1553+, implemented in 1.2 V 65-nm CMOS technology occupying 115470 μm2 of area. It incorporates a synchronous back-end and host processor interface to a true dual port memory for faster memory accesses. Employing a majority-based sampling free-running decoder at its front-end and scaled-up protocol state machines in its control...
Stochastic decoding can be applied to Low-Density Parity-Check codes in order to achieve high throughput with less area. However, most architectures suffer from large decoding latencies, due to the mechanism of stochastic computation. In this paper, three novel strategies, including the LUT-based initialization, the posterior-information-based hard decision and the Bit-Flipping-based post processing,...
As the reliability of NAND Flash memory keeps degrading, Low-Density Parity-Check (LDPC) codes are widely proposed to extend the endurance of Solid State Drive (SSD). However, implementing powerful decoding algorithm such as soft min-sum algorithm with high decoding speed comes along with higher hardware cost. To achieve efficient hardware cost, we propose a multi-strategy ECC scheme which consists...
DRAM industry faces a grand challenge on continuing the scaling of storage node aspect ratio (A/R) to maintain the storage node storage capacitance. One viable option is to intentionally slow down the A/R scaling at the penalty of irreparable weak cells that cannot guarantee target data retention time under worst-case scenarios, and compensate the weak-cell- induced memory errors at the system level...
The Dynamic Compact Control Language (DCCL) provides a flexible and efficient way to marshall object-messages into very small datagrams. It is well suited to transmission over very low throughput links with small maximum transmission units, such as those commonly used in underwater (acoustic modem) and sea-surface (satellite) applications. DCCL provides a interface description language (IDL) and an...
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