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It has been a decade since the National Institute of Standards and Technology (NIST) has selected the Rijndael algorithm as the Advanced Encryption Standard (AES). Since then, AES becomes the new block cipher standard of US government. A couple of years ago, with the shift of the technological trend towards the power aware system design, low power AES architectures gain importance over area and performance...
High-speed hardware for Keccak, which was selected as a new standard hash function named SHA-3, was developed and its performance was evaluated against SHA-1 and −2 circuits through the use of various FPGA platforms. The results showed that Keccak is suitable for high-speed hardware implementations, but it is getting harder to implement on new FPGA devices, due to the current trends in architecture...
Testing and verifying wireless systems in a real world environments is a challenging but an important problem. This is particular true for the Joint Tactical Radio System (JTRS) where the modulation techniques are optimized towards environments that are difficult to reproduce (e.g., ship to plane, plane to satellite communications). Such cases necessitate a wireless channel emulator to facilitate...
Integrating FPGAs with a general purpose computer remains difficult, but recent efforts have resulted in open frameworks that offer a software API and hardware interface to allow easier integration. However, such systems only support static FPGA designs. With the addition of partial reconfiguration (PR) support, such frameworks can enable more effective use of FPGAs. Now, designers can incorporate...
This paper presents radix-4 and radix-8 Booth encoded modular multipliers over general Fp based on inter-leaved multiplication algorithm. An existing bit serial interleaved multiplication algorithm is modified using radix-4, radix-8 and Booth recoding techniques. The modified radix-4 and radix-8 versions of interleaved multiplication result in 50% and 75% reduction in required number of clock cycles...
We describe extending the hardware/software co-compiler Nymble to automatically generate multi-threaded (SIMT) hardware accelerators. In contrast to prior work that simply duplicated complete compute units for each thread, Nymble-MT reuses the actual computation elements, and adds just the required data storage and context switching logic. On the CHStone benchmark suite and a sample configuration...
Priority queues are abstract data structures where each element is associated with a priority, and the highest priority element is always retrieved first from the queue. The data structure is widely used within databases, including the last stage of a merge-sort, forecasting read-ahead I/O to stream data for the merge-sort, and replacement selection sort. Typical software implementations use a balanced...
Cryptographic hash functions have many security based applications, particularly in message authentication codes (MACs), digital signatures and data integrity. Secure Hash Algorithm-3 (SHA-3) is a new cryptographic hash algorithm that was selected on 2nd Oct '12 after a five year public contest organized by the National Institute of Standards and Technology (NIST), USA. This paper provides a unique...
Clock is fundamental to information flow in magnetic field-coupled logic. And to improve the throughput from magnetic field-coupled logic, the logic operation also needs to be pipelined. However, pipeline implemented with the existing clocking structure of magnetic logic generates a constraint on layout and overall area. In this paper we have discussed this constraint and possible solutions to this...
In recent years, the rapid growth of visible light communications (VLC) is driven the interest into new applications of this technology. While single-user VLC systems are widely studied in the literature, less attention is given to multiuser scenarios which are likely to be deployed. Thus, this paper studies a new low-complexity multiuser structure for indoor VLC systems using RGB channels. In this...
Software development becomes an important issue in today's MPSoC design. Due to the inherent non-deterministic behavior of MPSoCs, they are prone to concurrency bugs. Debugging tools for MPSoC may be grouped in the following classes: simulators, parallel software development environments, NoC debuggers. An important gap is observed concerning a complete NoC-based MPSoC: tools to inspect the traffic...
Polar codes are among the most promising error correction codes due to their ability to achieve the symmetric capacities of the binary-input discrete memoryless channels (B-DMCs). However, how to design successive cancellation (SC) decoders which can maximize the hardware utilization efficiency is still challenging due to the inherent serial nature of SC decoding algorithm. To this end, in this paper,...
This paper presents area-power efficient architectures for the lifting based Wavelet Packet Transform (WPT). Using Daubechies 6 as an example, three different approaches to the lifting scheme implementation are optimized. For higher level decompositions, a novel Fibonacci based technique to optimally compute the number of processing elements per level is presented. Comparisons between FPGA implementations...
This paper proposes an architecture for structured low density parity check encoder. The proposed architecture supports the limitation of input/output pins of field programmable gate array using division of information bits. The division of information bits generates latency of encoding. The proposed architecture does not store the required matrix for bit-wise multiplication and does not use cyclic...
Today, many embedded applications are real time systems. Therefore, besides correct functionality they have to guarantee execution time bounds. To put it in other words, an embedded real-time system needs a good worst case performance. Additionally, the power and energy consumption is of great importance. Usually dynamic power and frequency scaling techniques are used to ensure this goal. However,...
The interplay between pairs of critical factors such as performance, energy and reliability within modern computing systems has always been an interesting topic of study. However, studying the interplay of all three factors together in a many-core, multi-layer design setting has been a relatively recent undertaking. This work explores the practical problems encountered in such studies and introduces...
Synchronous dataflow (SDF) graphs are a widely used formalism for modelling, analysing and realising streaming applications, both on a single processor and in a multiprocessing context. Efficient schedules are essential to obtain maximal throughput under the constraint of available resources. This paper presents an approach to schedule SDF graphs using a proven formalism of timed automata (TA). TA...
The multiple-input-multiple-output (MIMO) technique is widely used in modern wireless communication systems because it greatly increases system capacity and improves communication reliability. However, MIMO detection is a challenging task. Sphere detection algorithms are preferred in practice as these can achieve bit error rate performances close to that of the maximum likelihood algorithm. Sphere...
Frequency table computation is a key step in decision tree learning algorithms. In this paper we present a novel implementation targeted for dataflow architecture implemented on field programmable gate array (FPGA). Consistent with dataflow model of computation, the kernel views input dataset as synchronous streams of attributes and class values. The kernel was benchmarked using key functions from...
Frequently, applications such as image and video processing rely on implementations of the Linear Projection algorithm with high throughput and low latency requirements. This work presents a framework to optimise Linear Projection designs that excel typical design implementations via a pre-characterisation of over-clocked arithmetic units. It is well known that the delay models used by synthesis tools...
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