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Belief propagation (BP) polar code decoder is well-studied from many aspects. This study proposes a hardware optimization to improve performance of polar BP decoder by modifying both processing element (PE) and early stopping criterion (ESC). PE is optimized by using high-speed parallel-prefix Ling adder instead of carry ripple adder and WIB ESC introduced in literature is optimized by removing unnecessary...
Convolutional encoder is widely applied in lots of wireless communication standards including 3G/4G mobile communications, DVB (Digital Video Broadcasting), IoT(Internet of Things) transmissions and so on. Therefore multi-standard Viterbi decoder design for the above receivers is a hot issue. In this paper, a reconfigurable high performance Viterbi decoder design is proposed for LTE, WiMAX, CDMA2000,...
In this paper, three different approaches are considered for FPGA based implementations of the SHA-3 hash functions. While the performance of proposed unfolded and pipelined structures just match the state of the art, the dependencies of the structures which are folded slice-wise allow to further improve the efficiency of the existing state of the art. By solving the intra-round dependencies caused...
RISC-V is a new open-source general-purpose instruction set architecture (ISA) developed by the University of California, Berkeley. It allows everyone to design their hardware circuits based on application characteristics and can be used in embedded devices, desktop computer and high-performance servers. In this paper, we use the RISC-V processor to design a fast network packet processing system....
We present Timestamp Order Preserving (TOP), a replicated state machine (RSM) protocol that exploits the synchrony of networks to provide high performance. TOP uses physical timestamp of synchronized clock as a consistent total order to achieve consensus. It keeps estimating the bounds of network latency and offset of synchronized clock to deduce the commit time for each operation. It adopts speculative...
The Internet of Things (IoT) constrained devices show the urgent need for low power data security hardware cores. This paper presents a power efficient AES Core fabricated in UMC 130 nm CMOS technology by using Faraday standard cells library. The maximum throughput of the proposed AES Core is up to 2.6 Gb/s consuming about 0.2148 mW/MHz at 1.2V. The Dynamic Voltage and Frequency Scaling (DVFS) technique...
In this paper, we proposed an improved true random number generator (TRNG), which comprises a low-bias hardware random number generator (HRNG) and a scrambler based on linear-feedback shift register (LFSR). The HRNG reduces both DC offset from the noise sources and offset voltage from the comparator to generate low-bias bitstream. The LFSR-based scrambler further reduces the bias to zero without sacrificing...
Many models of spiking neural networks heavily rely on exponential waveforms. On neuromorphic multiprocessor systems like SpiNNaker, they have to be approximated by dedicated algorithms, often dominating the processing load. Here we present a processor extension for fast calculation of exponentials, aimed at integration in the next-generation SpiNNaker system. Our implementation achieves single-LSB...
This article describes a new latch-based asynchronous resilient bundled data design template. In environments with normally distributed combinational delays, Sharp achieves 8% higher throughput than state of the art controllers in simulation.
This paper presents a family of FIFOs for clock-domain crossings. These designs are distinguished by an interleaved architecture for the control and data-paths. This approach eliminates most of the throughput bottlenecks in the FIFO design, allowing operation at well over 1GHz in a 65nm process using a standard ASIC design flow. Furthermore, these designs are low-latency: the fall-through time for...
Modular multiplication is a fundamental and performance determining operation in various public-key cryptosystems. High-performance modular multipliers on FPGAs are commonly realized by several small-sized multipliers, an adder tree for summing up the digit-products, and a reduction circuit. While small-sized multipliers are available in pre-fabricated high-speed DSP slices, the adder tree and the...
Most correspondence movement in today's Network on Chips (NOC) depends on switch for unstable memory based outlines. The NOC ought to be intended to effectively deal with the many-to-one correspondence design, information access to and from the directing controller. This paper rouse the utilization of partitioned system for steering and legitimize the power utilization and execution change is gotten...
In this paper we develop a synthesis flow for multi-rate systems modelled by SDF graphs with the objective of minimizing power consumption while satisfying the given throughput constraint and using as few asynchronous FIFOs as possible. A novel hybrid synchronous/asynchronous buffering mechanism to optimize computation power using self-timed scheduling and Globally Asynchronous Locally Synchronous...
Hierarchical temporal memory (HTM) is the model of the neocortex functionality, developed by Numenta, Inc. The level of implementation does cover only the subset of actual neocortex layers functionality, but, however, is sufficient to be useful in different domain areas e.g. for a novelty or anomaly detection. Numenta provides their implementation of the HTM for commercial or research purposes as...
The aim of this work is to describe three different architectural designs for AES cipher, which is a symmetric block encryption standard. The three architectures are oriented to different applications and are designed using different approaches, like pipeline structures and resource sharing. They also include an AMBA AHB interface, which is an open standard that defines the interconnection of blocks...
A novel ordinary differential equation (ODE) solver is proposed by using a stochastic integrator to implement the accumulative function of the Euler method. We show that a stochastic integrator is an unbiased estimator for a Euler numerical solution. Unlike in conventional stochastic circuits, in which long stochastic bit streams are required to produce a result with a high accuracy, the proposed...
This paper presents a new architecture for distributed arithmetic (DA) based Least Mean Square (LMS) adaptive filter with low hardware complexity and critical path. It is well known that for DA based adaptive filter, the throughput depends on critical path and number of clock cycles to produce the output. In the proposed technique, we maintained the same number of clock cycles using multiplexed look-up...
Timed Petri nets are commonly used for modelling and analysis of automated manufacturing systems, including batch or high throughput systems. This paper consider the cycle optimization problem for a deterministic timed weighted marked graphs under infinite server semantics. The problem aims to find an initial marking to minimize the cycle time while the weighted sum of tokens in places is less than...
Various state-of-the-art Network-on-Chip (NoC) architectures, employing either low-or high-radix topologies, have exploited the speed provided by on-chip wires — after appropriate wire engineering — to transfer flits over longer distances in a single clock cycle. In this work, motivated by the same principle of fast link traversal, we propose the RapidLink NoC architecture, which exploits said speed...
The latest IEEE WLAN 802.11ad standard guarantees the multi giga bit throughput which is highest in the Wireless LAN (WLAN) technology. The system designed for such high performance will pose enough design challenges to make them consume low power. This can however be achieved by adopting low power management and control block in the digital part of the System on Chip (SoC) like Medium Access Control...
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