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In this paper, a low voltage low power (LPLV) current output stage (COS) with high CMRR is proposed. A novel common mode feedback (CMFB) technique is exploited to provide high CMRR. That is done by summing the main common mode signal and its opposite polarity one which provides over 112 dB of CMRR in 0.18 μm CMOS technology of TSMC. The circuit operates with very low supply voltages of ±0.5 V and...
Much attention has been paid to dynamic circuits and multi-logic technology in current low power design. In this paper, a new structure and the design methodology of the ternary dynamic BiCMOS circuit has been proposed based on the structure of the ternary dynamic CMOS circuit. The circuits designed following this methodology have shown advantages not only in heavy integration density, low power,...
This paper introduces a practical system for improving efficiency of low power dc-dc converters regulated by digital voltage-mode PWM controllers. Depending on the input voltage, the controller adaptively changes the switching frequency, thus minimizing related losses while maintaining tight output voltage regulation and constraining electromagnetic interference (EMI) caused by the variable frequency...
A novel low-power successive approximation register is proposed. The new register is based on gating the clock when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 14 bits has been designed up to the layout level with 1V power supply in 90nm CMOS technology and...
The following topics are dealt with: device aging; analog integrated circuit; 3D integrated circuit; low power circuit; low power sensor; low power memories; lithography; digital design automation; noise-aware design; custom circuit design issue; FPGA; circuit verification; circuit validation; circuit test; circuit reliability; package and processor co-design; power integrity; system design consideration;...
This paper presents the design of a 12-bit 8MSamples/s (MSPS) current-steering digital-to-analog converter (DAC) using 0.13 μm CMOS technology. The proposed DAC has adopted a segmented architecture in order to achieve a minimized die area and optimized performance. The current steering network consists of binary weighted current sources for the 8 least significant bits (LSBs) and a unary current cell...
Energy performance requirements are forcing designers of next-generation systems to explore approaches to least possible power consumption. Scaling of power supply voltage is major factor to reduce the power consumption. Threshold voltage may be reduced to achieve higher drive current and hence better speed, but at the cost of increase in the stand-by power. The technique to achieve ultra low power...
In this work, a new MIN circuit for low voltage applications is presented. The approach uses a new low output impedance configuration which allows working with low power supply requirements. The circuit was simulated in PSpice and a chip prototype was fabricated and tested using CMOS AMI 0.5μm N-well technology.
Successive approximation analog-to-digital converters are very attractive to power-constrained applications due to the topology inherent energy efficiency. This converter architecture most often relies on digital controller circuit to guide the conversion algorithm, and this controller is reported to have an important impact on the overall power consumption, sometimes demanding roughly half the total...
The successive-approximation (SA) algorithm is traditionally used for low bandwidth applications because it requires n clock cycles or more to obtain n-bit resolution. However, the use of modern nanometer CMOS technologies and special design solutions overcome the speed limit, enabling conversion rates in the hundreds of MHz with very low power consumptions. This design uses the successive-approximation...
Recently it has been shown that frequency-translated BPFs offer high-Q filtering with their center frequency precisely controlled by a clock. To address the scalability concerns and to achieve the same level of integration as the zero or low-IF receivers, this paper propose a low-power process-scalable superheterodyne receiver with integrated high-Q filters. The receiver presented exceeds the requirements...
One of the most continuous trends in solid-state circuits is the decrease in power supply as a direct consequence of technology scaling. The fact that Vt does not scale linearly with supply voltage has encouraged several low-voltage design techniques recently. The received voltage level in a wireless power transfer system decays rapidly with distance and also medical portable systems are calling for...
This paper presents a 120GHz fully integrated 65nm low power (LP) CMOS transmitter that achieves data rates above 10Gb/s. At these high frequencies an extremely high bandwidth is available. This allows multi-gigabit-per-second communication which provides an answer to the ever-increasing demand for higher data rates in wireless systems. However, wideband modulation of a 120GHz signal in 65nm LP CMOS...
There is an increasing demand for more advanced and effective medical devices due to the interest on real-time personal home health monitoring. The electroencephalogram (EEG) is a common noninvasive method for various applications, such as the prediction of epileptic seizure and brain-computer interfaces (BCIs). A key component of an EEG monitoring systems is the acquisition circuitry with ultra low-power...
We present an integrated wirelessly powered glucose sensor allowing a functional active system on a contact lens. This sensor IC consists of power management, readout circuitry, wireless communication interface, and energy-storage capacitors in a standard CMOS process with no external components.
Recently, we start to see Wireless Sensor Network (WSN) solutions on the market, which are mostly based on 802.15.4 standard or Zigbee equivalent. Most of these solutions integrate an 8-bit to 32-bit low power microcontroller, one or multiple sensors and run on batteries. However, business is not yet there massively. Does it mean we need additional innovation to boost market adoption? The aim of this...
The proliferation of location-based applications inside various handheld electronic devices, such as mobile phones and internet tablets, demands the GPS system to have low power consumption, small form-factor and be co-located on the same device with other radio systems, such as cellular, BT, and WLAN. The conventional GPS solution often uses two SAW filters, before and after an external LNA, to meet...
In this paper, the authors demonstrate a standard cell-based circuit technique fully operational at supply voltages between 84 mV and 62 mV in standard 0.13 μm bulk CMOS depending on the area overhead invested. Supply voltage reduction is limited by the degradation of the on/off current-ratio of CMOS transistors with decreasing VDD, causing the leakage currents through the off transistors to be on...
A 2-6 GHz WiMAX Low Noise Amplifier (LNA) using active inductor as shunt peaking load in resistive feedback configuration is designed in 0.13-μm CMOS process. This low noise amplifier uses a single active inductor to achieve high gain and input matching which leads to a compact circuit. The simulations show a maximum power gain (S21) of 14.18dB, minimum noise figure (NF) of 2.44dB while the input...
These tutorials discuss the following: Integrated LC oscillators; Embedded Memories for SoC: Overview of Design, Test, and Applications and Challenges in the Nano-Scale CMOS; Ultra Low-Power and Low-Voltage Digital-Circuit Design Techniques; Layout - The Other Half of Nanometer Analog Design; DPLL-Based Clock and Data Recovery; Practical Power-Delay Design Trade-offs; Distortion in Cellular Receivers;...
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