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The target of this work is to develop a low-power 39.25MHz crystal oscillator (XO) with low phase noise for RF applications and to achieve the highest FOM in XO's. To reduce the supply current at a constant negative resistance (RN) in the XO, a stacked-amplifier crystal oscillator (SAXO) operating at I/O voltage is proposed, eliminating the need for a Low-Dropout Regulator (LDO). By stacking 4 amplifiers,...
A full adder circuit is considered as one of the basic building blocks of Digital Signal Processors (DSPs), Arithmetic and Logic Units (ALUs), Application Specific Integrated Circuits (ASICs) and many other digital circuits and systems. Today, efficient full adder circuit design is one of the main challenges for VLSI engineers. This paper proposes a novel 1-bit full adder circuit designed using N-MOS...
A voltage mode (VM) biquadratic universal filter using a current controlled differential difference current conveyor transconductance amplifier (CCDDCCTA) is discussed. The proposed filter uses two capacitors and one CCDDCCTA block only. It has following important facets: (i) Low pass (LP), band pass (BP), high pass (HP), notch and all pass (AP) voltage responses using same configuration, (ii) All...
In vivo recording of neural action-potential (AP) and local-field-potential (LFP) signals requires the use of high-resolution penetrating probes. Driven by the need for large-scale recording and minimal tissue damage, a technology roadmap has been defined for next-generation probes aiming to maximize the number of recording sites while minimizing the probe dimensions [1]. In this paper we present...
This paper proposes a PLL architecture targeting ZigBee (ZB) and Bluetooth LE (BLE) band. It employs a single-well, direct back-gated Quadrature Voltage Controlled Oscillator (QVCO). An efficient, Integer-N, Multi Modulus Divider (MMD) using True Single Phase Clock (TSPC) logic is incorporated in the design to minimize the overall PLL power consumption. The QVCO gives phase noise of −110 dBc/Hz at...
In this paper the design of a voltage-mode switching mode amplifier in a 65-nm CMOS process in the GHz range is described. The amplifier can be operated with a rectangular drive signal with 50 % duty cycle up to 4 GHz and pseudo random bit sequences up to 4 GBit/s. The calibrated broadband PAE of the amplifier chip is 22 % at 2 GHz, 13 % at 3 GHz and 7 % at 4 GHz for a rectangular drive signal with...
In this paper, a 65-nm CMOS amplifier MMIC operating around 265 GHz is presented. To obtain a small signal gain of the amplifier in a frequency region close to Fmax (Maximum oscillation frequency) of a transistor, a neutralization technique of a feedback capacitance as well as a transistor model to neutralize it precisely are needed. For this purpose, the key is a de-embedding technique. To extract...
A dual-gate ion-sensitive field-effect transistor (DGFET) with the back-side sensing structure implemented in a 0.18 μm SOI-CMOS SoC platform realizing high performance bioelectrical detection with non-ideal effect reduction is presented. Non-ideal effects of the conventional ISFET, such as time drift and hysteresis, are suppressed by the innovative scheme in DGFET using the bottom poly-gate (PG)...
The Adder is the important part in any processor/controller design. Till date there are a plenty of 1-bit full-adder circuits which have been proposed and designed. In this paper we have a analytic and comparative description of various full adder circuits, considering various constraints like power consumption, speed of operation and area. The circuits are designed in the virtuoso platform, using...
A new high performance OTA circuit using a bulk-driven differential input stage and a flipped-voltage follower current mirror is presented. The proposed OTA is operated at low supply voltage of ± 0.4V with a reduced power consumption of 0.44mW. All simulations are performed by ELDO technology CMOS TSMC 90nm which is provided a good linearity over the dynamic range, wide bandwidth and an excellent...
Operational amplifier is an important portion of various analog and mixed signal circuits. Today use of mixed mode integrated circuits rises. Analog circuits particularly operational amplifiers in CMOS technology are difficult to design due to challenging and time consuming tasks like counting various conflicting benchmarks and a wide variety of design factors. This paper presents the use of Particle...
Modern day technology has extended its reach below 20 nm. All kinds of effects are to be seen in MOS devices due to different leakage mechanisms at deep sub-micron levels. These lead to errors in the system. Error tolerance (ET), an emerging concept in the field of VLSI design and test: by easing the restriction on accuracy, can be used to have improvements in speed and power depending on the amount...
In this paper, a high speed Differential Cascode Voltage Switch Logic (DCVSL) architecture has been proposed. Conventional DCVSL has higher τPLH than τPHL which limits its switching speed. Use of resistive enhancement technique, DCVSL-R can overcome the inherent delay asymmetry problem of DCVSL but the passive resistors used increase its parasitic capacitances as well as require more physical area...
This paper proposes a configurable logic block (CLB) for the efficient circuit realization in positive feedback source coupled logic (PFSCL) style. The proposed CLB incorporates the advantageous features of the PFSCL style and triple-tail cell concept. The operation of the new CLB is explained and the realization of different circuits by configuring the block is discussed. The efficiency of the proposed...
In this paper, low voltage low power highly linear operational transconductance amplifier (OTA) using source-degeneration technique is presented. Source-degeneration techniques improve the bias current of the input differential pair when large signals are applied, thus, increasing circuit dynamic characteristics without affecting stand-by dissipation. The OTA is designed to operate with a ±0.55V supply...
This work presents a process, voltage and temperature (PVT) invariant tunable voltage reference generator in 180 nm CMOS technology. Using weighted averaging of tuned PTAT and CTAT voltages at zero temperature coefficient point, the proposed design exhibits only ±0.28% variation in post-layout simulation across process corners over a temperature range of-25 degree C to 100 degree C. Maximum deviation...
A low voltage, low power CMOS down-conversion mixer is presented for Ultra-wideband (UWB) systems. The proposed mixer is designed for a 3.35 GHz input RF signal and 250 MHz output IF signal in 0.18pm CMOS technology and simulated using Advanced design system (ADS) software. The proposed mixer is based on the conventional Gilbert cell architecture with bulk driven technique. Two element LC matching...
Sigma-Delta Analog-to-Digital converter (ADC), is widely used in portable electronic products. An operational transconductance amplifier (OTA) is one of the most important components of this ADC. This paper reports a new design of low power fully differential OTA. In this design authors have used adaptive biasing technique and DC gain enhancement technique for improving design parameters as compared...
In this paper, a 2.4 GHz CMOS low noise amplifier (LNA) for wireless sensor network (WSN) application using CMOS 0.13-µm Silterra technology is presented. The proposed design employed two-stage forward body bias technique with cascode configuration in order to obtain ultra-low power LNA design with high gain. The simulation results show that the total power consumed is only 0.49 mW at low supply voltage...
This paper proposes the wideband active power splitter design where the gain cells are arranged in interleaf rather than the conventional parallel style. By reducing the shunt capacitance of the input transmission line, thus extending its bandwidth, the circuit's high-frequency performance can be greatly improved. A DC-40GHz interleaf active power splitter is then designed using 90nm-CMOS process...
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