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Array processors, and vision chips in particular, have mostly been designed from maximum processing speed point of view. There are applications in e.g. surveillance field, where the image content is analyzed rather rarely and where on the other hand the power consumption is of greater importance due to battery operation functionality. In sensing applications it is customary to use a coarser sensing...
With the introduction of the Internet of Things (IoT), power consumption became a major design issue in modern system-on-chips. In advanced technologies, leakage power has become a dominant component, especially during sleep periods. Leakage mainly comes from volatile memory elements, e.g., flip-flops that cannot be power-gated in order to retain their states. Non-Volatile Flip-Flop (NVFF) using emerging...
This paper presents a new method for ring amplifier biasing to improve their stability while maintaining high slew rate. A multi-path ring amplifier is proposed for switched capacitor applications that allows accurate charge transfer at high speeds. Dynamic biasing improves large signal slewing without affecting residue amplifier settling performance. Stable operation is possible because the auxiliary...
A novel solution of a single-stage buck-boost inverter with unfolding circuit at the output stage is presented. The inverter has a wide range of input voltage regulation, minimum passive components and a very flexible control structure. It can be applied for renewable energy systems where high power density is required. Our simulation results confirmed all theoretical statements.
Using a pulse density modulation (PDM) to regulate a load current of a resonant voltage-source inverter causes fluctuation of a current amplitude. The paper proposes a software phase-locked loop (SPLL) of control system in a resonant voltage inverter with PDM for induction heating equipment. The proposed SPLL changes a dead-time between control pulses of inverter transistors, taking into account current...
The topologies of voltage source inverters implicated now and in future for the needs of induction and traction frequency converters are considered. The two-level and three-level clamped diodes voltage source inverters are shown to be an optimal choice due to a number of reasons. The equations for numerical and analytical approaches of power losses evaluation are analyzed. The power losses evaluation...
Advances in power electronics devices and materials are creating opportunities to improve both machine and drive design in order to obtain better overall system performance by designing each to exploit the advantages available from technology development in the other. In order to combine wide-band-gap devices with novel machine designs that can benefit from their application, guidance about the interactions...
This treatise deals with Transistor Clamped Five Level Inverter using Non-Inverting Double Reference Single Carrier PWM (NIDRSC PWM) Technique. Conventional or two level inverter have drawbacks like: i) Requirement of fast switching devices, ii) Very high dv/dt, iii) High Electromagnetic Interferences (EMI), iv) Bulky filters, v) Faster heating of switches, and vi) Not suitable for high voltage applications...
This paper compares two CMOS technologies, the robust 350nm version and its modern 28nm successor, in terms of time-domain signal processing parameters. The evaluated parameters; propagation delay, delay variation due to process and mismatch fluctuations, sensitivity to noise and area and power usage are crucial especially in measurement devices relying on precise timings, high precision time-to-digital...
Model Predictive Control (MPC) method is proposed in this paper applied to a single phase grid-connected inverter. This method uses a state-space equation of the system to predict the next time value of current from the grid side by adjusting the duty ratio of inverter in each sampling period. The duty ratio which minimizes a cost function is selected. Then, taking advantage of the duty ratio to control...
This paper presents the development of a hybrid Class-E synchronous rectifier for wireless powering of quad-copters through inductive power transfer. A synchronous rectifier relaxes the heatsink requirement for continuous operation as the transistor conduction losses will be lower than the diode conduction losses. This provides an advantage when the weight of the electronics is significant for the...
In recent years, SRAM-based and other Weak PUFs have found applications in tamper sensitive key storage and ID generation. SRAM-based PUFs, for example, rely on intrinsic process variations to enable repeatable and unique start-up behavior of their outputs. However, noise in the system can compromise repeatability of SRAM start-up behavior. To obviate this problem, a number of solutions such as fuzzy...
This paper presents a brief overview of Schmitt Triggers and proposes a low voltage adjustable CMOS Schmitt trigger using body biasing technique. The voltage-feedback inverter with body control is employed to speed up the switching process, and control the intensity of the feedback. The proposed Schmitt trigger makes it particularly attractive for low-voltage high-speed applications. The CMOS Schmitt...
In this paper, we have designed a β driven 1-bit full-adder circuit. Circuits based on threshold elements have raised extensive interest in recent years. It uses a CMOS(complementary metal oxide semiconductor field effect transistor) pair with variable β. Transformation of a regular analytic representation of the threshold function in a ratio form is the concept behind the design of the β driven circuit...
The parameters such as Write Delay, Read Delay, Leakage Power, assumes an imperative part in the present day CMOS innovation. This paper examined about the near investigation of different SRAM cells, for example, 6T, 5T and 4T utilizing 22nm innovation. At the point when looking at 6T and 4T, the 4T SRAM cell has the efficient output. The leakage power is reduced considerably in 5T SRAM cell. This...
The cascaded asymmetrically sized inverters can be employed as pulse stretchers, for the measurement of very short single event transient (SET) pulse widths (< 200 ps). This paper analyzes, through the circuit simulations, the effects of various design and operating parameters on the normal operation and SET robustness of a two-inverter pulse stretcher designed in 250 nm bulk CMOS technology. It...
The rate of aging of ICs is increasing with the continued reduction in feature sizes of devices. Bias temperature instability (BTI) is considered to be the major reliability hazard in nano-scale CMOS and causes stability degradation of SRAM cells. Some of the SRAM cells functioning properly at fabrication may fail during their desired lifetime due to aging. This will cause large aging quality loss...
Hot carrier induced degradation of MOSFETs is still a concern for circuit reliability and not yet fully understood [1-4]. On the one hand stress measurements at single devices reveal critical parameter degradation for modern technologies especially at high VD=VG. On the other hand there are several publications stating that at least for combinational logic HCS plays only minor role for lifetime limits...
Background/Objectives: In the contemporary era, due to the rapid development in various low power VLSI circuits, the primary factors that affect the performance of the circuits are gaining much importance. The static random access memory (SRAM) is one of the significant circuits employed in low power VLSI systems. Many researchers continue focusing on efficient SRAM designs and towards increasing...
Background: Multiple-Valued Logic (MVL) is the non-binary-valued system, in which more than two levels of information content are available, i.e., L>2. In modern technologies, the dual level binary logic circuits have normally been used. However, these suffer from several significant issues such as the interconnection considerations including the parasitics, area and power dissipation. The MVL...
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