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Performance degradation of memory-intensive programs caused by the LRU policy's inability to handle weak-locality data accesses in the last level cache is increasingly serious for two reasons. First, the last-level cache remains in the CPU's critical path, where only simple management mechanisms, such as LRU, can be used, precluding some sophisticated hardware mechanisms to address the problem. Second,...
Many recent visual recognition systems can be seen as being composed of multiple layers of convolutional filter banks, interspersed with various types of non-linearities. This includes Convolutional Networks, HMAX-type architectures, as well as systems based on dense SIFT features or Histogram of Gradients. This paper describes a highly-compact and low power embedded system that can run such vision...
This paper presents a video shot boundary detection system based on support vector machine (SVM) classification method. A hardware fully-parallel digital support vector machine (SVM) classifier is used to detect the shot boundary in a continuous video stream. The throughput is increased by employing a pipelined architecture in the feature extraction stage. Hardware SVM can detect both cut and gradual...
A central issue in computational intelligence is the training phase of a learning machine. In classification problems, in particular, Support Vector Machines are one of the most effective tools. In this work an analog low-complexity circuital implementation is proposed to address the learning stage of SVMs. The circuit is a co-content minimization network based on a suitable SVM formulation embedding...
Remote attestation of system integrity is an essential part of trusted computing. However, current remote attestation techniques only provide integrity proofs of static properties of the system. To address this problem we present a novel remote dynamic attestation system named ReDAS (Remote Dynamic Attestation System) that provides integrity evidence for dynamic system properties. Such dynamic system...
We propose an analog circuit architecture of the Gaussian-kernel support vector machine having on-chip training capability. Thanks to the hardware-friendly algorithm, the learning function is realized by attaching a small additional circuitry to the SVM classifying hardware. Though the system works as analog circuits, the input and output signals including training results are all available in digital...
Support vector machines (SVMs) are powerful, state-of-the-art machine learning tools. With the aim to integrate SVM training capability into embedded systems while being able to meet area and performance constraints, a parallel and scalable digital architecture for training SVMs on-line is proposed and implemented on a field-programmable gate array (FPGA). Experiments show that the proposed SVM processor...
In this work we show that a metaheuristic, the variable neighborhood search (VNS), can be effectively used in order to improve the performance of the hardware-friendly version of the support vector machine (SVM). Our target is the implementation of the feed-forward phase of SVM on resource-limited hardware devices, such as field programmable gate arrays (FPGAs) and digital signal processors (DSPs)...
This paper presents the SISLOC project. This project aims at developing a FPGA-based speaker verification system that is able to authenticate a personpsilas identity by analyzing speech samples. The hardware implementation of a system like that provides many advantages, when compared with a software counterpart: better scalability, lower final cost and possibility of reconfiguration, among others...
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