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We describe a new pseudorandom generator for AC0. Our generator $\epsilon$-fools circuits of depth and size and uses a seed of length $\tilde O( \log^{d+4} M/\epsilon)$. The previous best construction for was due to Nisan, and had seed length $O(\log^{2d+6} M/\epsilon)$. A seed length of $O(\log^{2d + \Omega(1)} M)$ is best possible given Nisan-type generators and the current state of...
Reed-Solomon (RS) codes are one of the most widely used block error-correcting codes in modern communication and computer systems. Multiplication is the key computation in RS encoding. Adopting the generator polynomial with symmetric coefficients, the number of multipliers in RS encoders can be reduced by half, and their power consumption may also reduce. However, in some cases, the encoder based...
To solve the problems of current polynomial estimation algorithms for PN sequence, such as insufficient efficiency and error-tolerance, a novel algorithm based on reliability accumulation is proposed combining BM iterative algorithm based on binary sequence with improved Chase algorithm. Using sequence soft information and constructing the sequence and corresponding polynomial reliability outside...
The following paper describes the statistical researches' results comparison of the Linear Feedback Shift Register (LFSR) and the Dynamic Linear Feedback Shift Register (DLFSR) generators. Obtained statistical researchers' results were compared and this comparison confirmed that DLFSR pseudo random sequences have better statistical properties. The statistical parameters of the pseudo random sequences,...
In this paper a detailed description of constructive algorithms aimed at generating controllable nilpotent systems is presented. Exemplary nilpotent systems with varied degree of nilpotency, number of generators and state space dimensionality are provided. Some combinatorial questions concerning a structure of the systems are stated and answered. Nilpotent systems can serve as useful models for practical...
This article consists of two parts: a theoretical part concerned with fault detection schemes, and an application part dealing with cyber security of power systems. In the first part, we develop a tractable approach to design a robust residual generator to detect and isolate faults in high dimensional nonlinear systems. Previous approaches on fault detection and isolation problems are either confined...
Cyclic Redundancy Check (CRC) is a well known error detection scheme used to detect corruption of digital content in digital networks and storage devices. In this paper, we present a study of different approaches of designing highly adaptable co-processors for CRC on an FPGA which are used in many network and server applications. The results of our research are two new architectures: adaptable and...
We present a hardware architecture for efficient implementation of a Gaussian random number generator (GRNG), using the Monty Python method. To maximize the performance/complexity efficiency, an efficient word-length optimization model is proposed to find out both the optimal integer and fractional word-lengths for signals. Experimental results show that our optimized Fixed-Point design achieves a...
Instances of control systems are presented for which dynamical feedback linearizability can be assessed from differential forms of highest relative degree after some “contact” transformation has been applied. This bypasses the need to find a polynomial differential operator that leads to an integrable co-distribution.
In this paper we consider the problem of tracking reference signals modeled by splines on the output of an uncertain linear system. The problem is cast in the hybrid output regulation setting. We show that any spline-based signal can be generated as the output of a linear hybrid exosystem that experiences jumps regularly over time. Then, we design a hybrid internal model-based regulator able to guarantee...
The scrutiny of the class of Reed-Solomon (RS) based quasi-cyclic (QC) low-density parity-check (LDPC) codes has inspired the authors to propose a memory efficient mirror-paradigm (MP) RS-based QC-LDPC code by exploiting the geometrical properties from the RS-based QC-LDPC nomenclature. Without any loss in performance, the proposed MPRS-based QC-LDPC code delivers discernible memory savings that address...
This paper proposes an efficient and secure identity based online and off-line aggregate signature scheme with random oracles. An aggregate signature privides a technique for combining n differents signatures of n different messages into one signature of constant length. The proposed scheme can be implimentated on Wireless Sensor Networks application. Security of the proposed scheme is based on difficulty...
The problem of efficient evaluation of the discrete Fourier transform over finite fields is considered. The techniques for additive complexity reduction of the cyclotomic FFT algorithm are proposed. The first one is based on the classical simultaneous reduction algorithm. The second one is based on a factorization of the presummation matrix into a sparse and block-diagonal ones. The proposed methods...
We provide a characterization of “pseudoentropy” in terms of hardness of sampling: Let (X;B) be jointly distributed random variables such that B takes values in a polynomial-sized set. We show that no polynomial-time algorithm can distinguish B from some random variable of higher Shannon entropy given X if and only if there is no probabilistic polynomial-time S such that (X; S(X)) has small KL divergence...
The AAL2 of ATM switching system uses the cyclic redundancy check code(CRC) to correct one bit error of the Common Part Sub-layer payload head(CPS-PH). Heavily based on CRC principle, in this paper analyses the process of one bit error correction of the CPS-PH is explored in detail.
Abstract-ATM Adaptation Layer type 1 (AAL1) that can be divided into the Convergence Sublayer (CS) and Segmentation and Reassembly (SAR) sublayers is designed to provide the class A traffic of ATM layer. The AAL1 SAR Protocol Data Unit (PDU) header uses Cyclic Redundancy Check (CRC) and even parity to detect and correct errors. After describing the encoding rules of the CRC and parity-check, this...
An improved stream cipher based on the linear feedback shift register is set up by adding disturbance on to the initial states. The key advantage of the new algorithm over the already proposed ones is that the characters of the ciphertext corresponding to the same characters in the plaintext are distinct. The new algorithm also keeps all other advantages. Therefore, for the adversary, it is more difficult...
Generally, the major part of communication systems use Turbo Codes (TC) and/or Low-Density Parity-Check (LDPC) codes to protect the data to transmit (e.g. 3GPP-LTE, IEEE 802.11p, IEEE 802.16, etc). Given that these coding strategies share similarities (e.g. two stage iterative decoding, Log-Likelihood Ratio based, etc.) in their respective encoding and decoding parts it is possible to express one...
This paper describes and compares two scrambler architectures developed and implemented in an advanced field programmable gate array (FPGA), with applications in 100 Gbit/s optical transport network (OTN) systems.
This paper describes a design for a variable fractional delay (VFD) FIR filter implemented on reconfigurable hardware. Fractionally delayed signals are required for several audio-based applications, including echo cancellation and musical signal analysis. Traditionally, VFD FIR filters are implemented using a complex, fixed structure based upon the order of the filter. This fixed structure restricts...
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