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The main objective of this paper is to implement a multiplier for high speed and low energy applications. Multipliers are the building blocks of high performance systems like FIR filters, Digital signal processors, etc in which speed is the dominating factor. There are many multiplier architectures developed to increase the speed of algebra. Booth algorithm is the most effective algorithm used for...
This paper describes the systematic design of a high speed and high resolution CMOS Flash Analog-To-Digital Converter. A 7-bit flash ADC is implemented in cadence environment using gpdk90-nm CMOS technology with a 1.2-V analog supply voltage. The converter achieves a signal-to-(noise + distortion) ratio of 39.3574dB and signal-to-spurious-free-dynamic-range of 40.7547dB with a sampling rate of 500MHz.
A multi-core machine has more than one execution unit per CPU on single motherboard. With the advent of multi-core machines parallelization has become an essential part in recent compiler research. Parallel parsing is one of the areas that still needs significant work to utilize the inherent power of multi-core architecture. This paper presents an algorithm that performs parallel syntax analysis of...
A digital additive white Gaussian noise (AWGN) generator has recently become a public focus with the increasing demand of hardware simulation in researches on communication discipline. Some successful ideas of software, such as the Box-Muller method, are then proposed and implemented into hardware platforms and the architecture design has attracted new studies. Then high-precision small-error Gaussian...
We focus on improving resilience of cloud services (e.g., e-commerce website), when correlated or cascading failures lead to computing capacity shortage. We study how to extend the classical cloud service architecture composed of a load-balancer and replicas with a recently proposed self-adaptive paradigm called brownout. Such services are able to reduce their capacity requirements by degrading user...
Stream processing has emerged as an important model of computation in the context of multimedia and communication sub-systems of embedded System-on-Chip (SoC) architectures. The dataflow nature of streaming applications allows them to be most naturally expressed as a set of kernels iteratively operating on continuous streams of data. The kernels are computationally intensive and exhibit large amounts...
Many-core architectures are becoming mainstream in both processor designs and System-on-Chip (SoC) designs. With the growing number of cores on a chip, Network-on-Chip (NoC) has become the de-facto on-chip communication infrastructure. Since it is believed that the near future many-core architectures will have thousands of cores integrated on a single chip, it is essential to have both full-system...
This paper presents results of a study to determine the most appropriate agent based architecture for implementation of controllers for stand-alone microgrids. The controller has to perform these main tasks: maintaining sufficient system voltage during supply overload conditions, balancing load flow, and managing voltage level in case of failure of some converters, or adding new converters to a system...
Data encryption is the primary method to protect embedded devices in the hostile environment. The security of the traditional data encryption algorithms relies on keeping the keys secret and they always require a lot of arithmetic and logical computations, which may be not suitable for area critical or power critical embedded devices. At TrustCom 2013, Hou et al. Proposed to use a physical unclonable...
Machine Translation System (MTS) that uses the Tree Adjoining Grammar (TAG) is considered. To improve the response time of our online MTS, we propose the use of a translation memory (TM). The integrated architecture of MTS with TM is outlined. Several examples of language dependent TM tools and translation process are given. To further speedup the translation process, we port MTS on a computing cluster...
Nowadays, the rapidly changing Information and Communication Technologies bring new opportunities to the e-learning field. One of these opportunities is the use of LMS (Learning Management System) platforms. LMSs have to be able to interact with external applications and thus reconfigure their functionalities. In this context, the present paper aims at proposing an approach for integrating external...
Although periodicity simplifies design and analysis in control theory, it is no more adapted for embedded and networked cyber-physical systems because it results in a conservative usage of resources. Indeed, the control signal is computed and updated at the same rate regardless whether is really required or not, and is periodically sent on the communication link. On the other hand, event-driven sampling...
The aim of this paper is to show that an accurate and efficient text classifier for relatively simple problem domains can be created in only a few hours of development time. The motivating example discussed in the paper is a recent HackerRank competition problem that tasked competitors with creating a classifier for questions from the popular question and answer platform StackExchange. The paper describes...
This paper proposes a low phase noise all-digital programmable DLL-based clock generator. The proposed clock generator is fabricated in a 0.18 μm standard CMOS process with a 1.8 V supply voltage. The proposed digital programmable DLL-based clock generator is easy migration over different processes and low power dissipation. The measurement results show that the input and output frequency ranges can...
Recent advances in the underlying architectures of database management systems (DBMS) have motivated the redesign of key DBMS components such as the query optimizer. Optimizers are inherently difficult to build and maintain, and yet there exists no software engineering tools to facilitate their development. In this paper, we introduce a [Devel]opment Environment for Query [Op]timizers (Devel-Op) designed...
In recent years of development in wireless communication many baseband processors been proposed in various fields in order to propel the demand of high performance, less effective area, this changes according to the need of future developments. This paper presents an efficient processor architecture framework with respect to power consumption and area. The proposed framework can accommodate basic...
This paper presents a hardware implementation of a digital watermarking system that can insert invisible watermark information into video streams in real time. The watermark embedding is processed in the integer based wavelet transformation, lifting and least significant bits approach. To achieve high performance, the proposed system architecture employs pipeline structure and uses parallelism. Hardware...
Simulation platforms for complex networked real time systems require random input pattern generators for simulating input distributions. They also require monitors for checking whether the output of the system satisfies the desired throughput. In this paper we study the acceptance and generation problems in a setting where the constraints defining the input distributions as well as the constraints...
In online model-based testing, test execution is interleaved with test generation. Test cases should be generated and executed with minimal delay, while still achieving targeted coverage criteria quickly. Extensive model analysis in such case is not possible as any delays in choosing the next step will immediately impact the response times of test execution. The algorithms thus need to be as fast...
This paper presents a design of 4-bit pipeline arithmetic logic unit (ALU). The novelty of the pipelined ALU is it gives high performance through the pipelining concept compare to non-pipeline ALU. Pipelining is a technique where multiple instruction executions are overlapped. The pipeline modules are independent of each other. All the modules in the ALU design are realized using verilog HDL. Design...
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