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Two important trends can be identified in parallel computing. First of all, the scale of parallel computing platforms is rapidly increasing. Secondly, the complexity and variety of current software systems requires to consider the parallelization of application modules beyond algorithms. These two trends have led to a complexity that is not scalable and tractable anymore for manual processing, and...
In this paper we introduce a dynamic GUI test generator that incorporates ant colony optimization. We created two ant systems for generating tests. Our first ant system implements the normal ant colony optimization algorithm in order to traverse the GUI and find good event sequences. Our second ant system, called AntQ, implements the antq algorithm that incorporates Q-Learning, which is a behavioral...
In this paper, a novel architecture for charging mode controller of Li-Ion battery charger is proposed. It is design to generate stable control signals even when noise level reaches several tens of millivolts. The trickle current is as low as 200mA enabling longer life cycle for Li-Ion battery. The large current reaches 1A without any impact on trickle current offering a faster charging time for Li-Ion...
This paper describes a specification language for platforms using contracts. We provide the intuitive explanation of what a contract-based platform is as well as the formal analysis. By using Satisfiability Modulo Theories tools, architectures or detailed designs derived from such platforms can be verified automatically. A tool is presented that allows users to design platform components and rules...
The paper presents the analysis of radiationinduced Single-Event Transients (SET) in Delay-Locked Loop (DLL) and its impact in the digital output of Time-to-Digital Converter (TDC). The performance of the TDC such as Differential Non-Linearity (DNL),Integral Non- Linearity (INL), resolution etc. are degraded due propagation of the SET from the DLL. The use of improved pseudo differential currentstarved...
In this project, reconfigurable hardware architecture is used for performing the polynomial matrix multiplications (PMM). Hardware architecture is designed by using the Xilinx system generator tool. System generator enables the use of the math works model-based Simulink design environment for FPGA design. For designing PMM system, Fast Fourier Transform (FFT) technique is used rather than Convolution...
The evolution of information technology and the explosive growth in Internet data have rendered traditional ways of providing information services and their infrastructure no longer appropriates. Data storage, computing and Internet services are moving toward virtualization and cloud computing. However, the performance of this network architecture needs to be examined to improve network bandwidth...
This paper presents a Software Radio implementation for an Electric Arc locator system. The novelty of this work resides in the application of telecommunication specific signal processing methods for the field of energy generation and transmission. The advantage of the proposed solution compared to other current implementations is the improved flexibility and adaptability to various working conditions...
This paper shows a novel concept of the Reed Solomon (RS) codec IP generator for produce ten kinds of RS codec including RS(28,24), RS(32,28), RS(36,22), RS(72,64), RS(182,172), RS(204,188), RS(207,187), RS(208,192) [1], RS(255,223) [2] and RS(255,239) for targeting various communication standards and systems which use Reed Solomon (RS) codes. The RS codec IP generator will perform the hardware design...
This work is based on two major areas, the Multiview Service Oriented Architecture and the combination between the computing cloud and MVSOA. Thus, it is suggested to extend firstly the service oriented architecture (SOA) into an architecture called MVSOA by adding two components, the Multiview service generator, whose role is to transform the classic service into Multiview service, and the data base,...
This paper presents a hybrid multimode Bose Chaudhuri Hocquenghem (BCH) encoder for reducing the input length of Syndrome calculation (SC) based on re-encoding approach. In previous re-encoding approaches, a conventional BCH encoder with long generator polynomials is used as a remainder operator to reduce the input length of SC. However, the input length is still large since long polynomial is used...
Polar codes have emerged as the most favorable channel codes for their unique capacity-achieving property. To date, numerous approaches for efficient decoding of polar codes have been reported. However, these prior efforts focused on design of polar decoders via deterministic computation, while the behavior of stochastic polar decoder, which can have potential advantages such as low complexity and...
Physically Unclonable Functions (PUFs), exploit inherent manufacturing variations and present a promising solution for hardware security. They can be used for key storage, authentication and ID generations. Low power cryptographic design is also very important for security applications. However, research to date on digital PUF designs, such as Arbiter PUFs and RO PUFs, is not very efficient. These...
This paper presents a modified dynamic bus arbiter architecture for a system on chip design. A high performance SoC communication architecture based on probability bus distribution algorithm where all masters request are having same priority. However, the arbitration plays a critical role in determining performance of bus distribution based system. When all masters generate the request to access the...
The cyclic redundancy check (CRC) is a popular error detection code (EDC) used in many digital transmission and storage protocols. Most existing digit-serial hardware CRC computation architectures are based on one of the two well-known bit-serial CRC linear feedback shift register (LFSR) architectures. In this paper, we present and investigate a generalized CRC formulation that incorporates negative...
A generator modulo 3 (mod 3) is a circuit that generates a residue mod 3 from a binary vector. It is an essential circuit used to construct the encoding and checking circuitry for arithmetic error detecting codes, such as residue codes mod 3 and the 3N code, as well as some residue number system hardware. In this paper, we compare speed and area of varius VLSI implementations of 16-input generators...
A high performance table-based architecture implementation for CRC (cyclic redundancy check) algorithms is proposed. The architecture is designed based on a highly parallel CRC algorithm. The algorithm first divides a given message with any length into bytes. Then it performs CRC computation using lookup tables among the divided bytes in parallel. At last, the results are XORed to obtain the CRC value...
This paper presents a novel concept for increasing the penetration level of distributed renewable energy systems into the main electricity grid. When increasing the renewable energy penetration, it is important to implement the frequency based power delivery in distributed generators and work as traditional synchronous generators. This can be achieved by improving the power processing unit of each...
Processor development is done in stages. It is a safe bet if we start by modeling the processor at a high level of abstraction, perform refinements at high level, and when we are satisfied by the performance, go into manufacturing. The process of refinement is done by evaluating the design criteria. This process generally goes through a cycle that can be described as Design Space Exploration (DSE)...
The technique of Test Sequence Generation (TSG) plays a key role in Built-In Self-Test (BIST) architecture implementation. Major problem with any test sequence generator is to produce long, unpredictable key sequences which can be applied to Circuit Under Test (CUT) in order to detect the faults efficiently. Digital Systems/Circuits are tested by inducing appropriate stimuli and checking the responses...
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