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In this study, the influence of sidewall thickness on the threshold voltage and on-current of L-shaped Impact-ionization metal-oxide-semiconductor transistor (I-MOS) is investigated. For the sidewall thickness in the range of 10 nm to 20 nm, the devices of thicker sidewall show lower on-current and higher threshold voltage. This is because the electron concentration between the channel and the most...
Poly-Si TFTs with vacuum cavity next to the gate-oxide edge (quasi T-gate TFTs) have been fabricated with the wet-etching of gate-oxide and in-situ vacuum encapsulation techniques. The device characteristics of the quasi T-gate TFTs are examined and better than those of conventional TFTs, resulting from the vacuum cavity as the offset region to reduce the leakage current and as the field-induced drain...
Long-term field-reliability of gallium nitride (GaN) and silicon carbide (SiC) power switching devices is critically discussed in terms of bulk material defects. A new static reverse bias stress test circuit with a reactive load is proposed to delineate devices prone to field-failures.
Reliability and compactness are two aspects often fighting among themselves when speaking about power electronics, but, indeed, they are the keys for the success of any new circuit or device. Reliability, in particular, is the word of the moment, powering the development of advanced device design techniques having the reliability as a major goal. Endurance tests is the traditional way to evaluate...
Defects and the yield loss associated with them have plagued semiconductor fabs since the dawn of the industry. Research has shown that contamination is responsible for up to 75% of the yield loss in integrated circuit fabrication. A single defect can destroy an entire die by creating a short in a junction region or cause an open circuit in a gate electrode of a device. Defects can also degrade device...
The electrical characteristics and reliability of HfO2-based p-GaAs metal-oxide-semiconductor (MOS) capacitors (EOT: 2.4 nm to 4.8 nm) with a thin Silicon (Si) interfacial passivation layer (IPL) have been investigated with different thicknesses of HfO2. SILC generation kinetics and flat band instability were investigated via CVS and CCS measurements. In addition, breakdown voltages of gate oxide...
The intermetallic compound (IMC) growths of Cu pillar bump with shallow solder (thin Sn thickness) were investigated during annealing or current stressing condition. After reflow, only Cu6Sn5 was observed, but Cu3Sn formed and grew at Cu pillar/Cu6Sn5 interface with increasing annealing and current stressing time. The kinetics of IMC growth changed when all Sn in Cu pillar bump was exhausted. The...
The performance and reliability of 3-D NAND cells fabricated by TCAT (Terabit Cell Array Transistor) technology have been improved significantly via a damascened metal gates and a controlled offset between BL contact and select transistor. The damascened metal gate providing sufficiently low resistance is achieved by adopting a novel metal process. Highly suppressed disturbance property is achieved...
Flip-chip packages are currently used for various applications such as desktop computers, servers, gaming, telecommunications, etc. Due to tremendous demand of die functionality, the power levels and more importantly the die heat-flux densities are drastically increasing, thus customers are constantly pushing packaging industries to lower thermal impedance of TIM for very high power flip chip packages...
High bandwidth junction temperature measurement provides a key signal for active thermal control to improve reliability of power electronics. Recently developed isolated techniques to estimate junction temperature from the decay of turn-on ringing depending on circuit properties are not well documented in existing circuit models. This paper focuses on how to develop circuit models that are suitable...
The following topics are dealt with: thermal interface materials; device level thermal management and LED cooling; single phase liquid cooling; data center cooling and phase change materials; two phase liquid cooling; thermoelectronics and refrigeration; heat pipes; heat conduction; transient heat transfer; chip cooling and stacked dies; reliability; microfluidics; and nano-enhanced thermal management.
The reliability of sub-micrometers InP-based heterostructure bipolar transistors (HBTs), which are being applied in over-100-Gbit/s ICs, was examined at high current injection conditions. These HBTs had a ledge structure and an emitter electrode consisting with a refractory metal of W, which suppressed surface degradation and metal diffusion, respectively. We conducted bias-temperature (BT) stress...
Current collapse (drain current dispersion, gradual power saturation, or memory effect) encountered during microwave GaN HEMT power amplifier operation remains to be a major reliability and stability issue for the highly promising, emerging III-nitride, polar semiconductor based technology. Current collapse leads to bias condition induced memory effect, which is particularly detrimental to broad band...
High-resistance via explosion is a new damage phenomenon which is induced during TEM sample preparation using FIB. Two methods that will prevent this phenomenon are introduced. In practice, these methods have been effective in avoiding high-resistance via explosion.
Wafer level reliability (WLR) issues of DRAM cell and peripheral transistors are discussed. Since the 70 nm technology node, recessed transistors have been accepted for assuring data retention time of DRAM cell transistors. Various recessed transistor structures suggest that the most important issue in reliability, in addition to optimizing data retention time, is the elimination of local regions...
In this paper, we study thermal disturbance and its impact on reliability using a novel measurement structure - the micro-thermal stage (MTS). The small thermal time constant of the MTS extends the time-scale of temperature dependence measurement to ~100 μs. The reliability of phase-change memory (PCM) is evaluated in terms of data retention and variation of the high resistance (RESET) state resistance...
A systematical reliability assessment for technology process that is essential for technology feasibility and qualification is presented by addressing physical and electrical characterization and reliability evaluation. By varying the duty cycle of enhanced pulsed radio frequency (eprf) technique used for the gate oxynitridation, the effects of nitrogen concentration and profile at SiO2/Si interface...
The spatial distribution of multiple breakdown (BD) spots in large area MOS structures was investigated. By means of applying image processing and point pattern analysis techniques we provide for the first time direct evidence that the BD spots' locations are spatially uncorrelated as expected for a Poisson process. For completeness, we show how the available mathematical tools might be utilized to...
The dielectric reliability of devices operating in the high bias, low gate current sub threshold state that can occur in analog and mixed signal designs is investigated using substrate hot carrier injection to accelerate breakdown. The complexities of this stress mode are elucidated and a reliability projection methodology is presented.
Pre-existing void effect during electromigration in a sub-30nm wide Cu interconnect was observed. Two types of void are intentionally produced in a single damascene interconnect: 1) A void between Cu and capping dielectric layer (center void) is mainly produced from an excessive overhang by depositing a thick seed layer. 2) A void between Cu and barrier metal (side void) is produced from depositing...
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