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A new type of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with self-aligned metal electrodes (SAME) is systematically characterized. New device features different from conventional poly-Si TFTs are found, and are attributed to the presence of Schottky barriers at the channel ends.
A new method for extraction of series resistance is proposed for poly-Si thin-film transistors. In this method, the extraction procedure is insensitive to the variation in effective channel length and device mobility, since both quantities are included in a single extracted parameter. The method has been successfully applied to a group of poly-Si TFTs with mask channel length from 2 to 30μm. Compared...
In this paper we study the variability induced by random discrete dopants in a gate-all-around silicon nanowire transistor. The electron transport is described using the Non-Equilibrium Green Function formalism. Coupled-mode-space representations are used. A silicon nanowire transistor with 4.2×4.2 nm2 cross-section and two different channel lengths (6 nm and 12 nm) has been considered. The mobility...
MOS-Triggered Silicon Controlled Rectifier(SCR) has been used as on chip Electrostatic Discharge (ESD) protection. However, the inherit slow turn-on speed is a major drawback of SCR. The compact MOS-Triggered SCR devices have been proposed and investigated in a 0.13μm CMOS process with the consideration of turn-on speed. From the test results, the turn on time of compact MOS-Triggered SCR has improved...
This work is about the development of a temperature-dependent driving strategy for power transistors, aimed at counterbalancing temperature related increases in their on-state resistance and power losses by a corresponding increase of the amplitude of the applied driving signal. The concept is first demonstrated on the example of a PowerMOSFET, based on semiconductor theory and circuit simulations...
New semiconductors materials like silicon carbide (SiC) and gallium nitride (GaN) offer as major benefits the possibility of constructing high-voltage switching devices characterized by very low conduction and switching losses. Most of the related research and development has nevertheless been focused on voltage classes like 600V and 1200V. For the referred levels it is expected that such new devices...
Hot carrier (HC) stress induced negative differential resistance (NDR) behavior in the reserve mode output characteristics of n-type poly-Si TFTs is first observed. The NDR phenomenon, i.e., ION decreases with increasing VD is also found to increase at higher VG but disappear when VG<;VTH and is reduced as stress time increases. Based on drain induced grain barrier lowering and thermionic emission...
We present an approach to scale Rext while maintaining control of short channel effects in scaled finFETs. For FETs with fins <;20nm, an enhancement of 19% in drain current was achieved in nFETs by incorporating Al at silicide-Si interface. This Al implantation while reducing the schottky barrier height for n-Si contact by 0.4 eV, does not degrade the integrity of the junction extensions or gate...
Power devices fabricated in 4H-SiC are poised to significantly impact the field of power electronics. There has been great interest in SiC as a material in which to fabricate power electronic devices for quite some time based on its very promising fundamental materials properties. However, it has been far more recently that the potential of SiC is being appreciated as a result of the recent advances...
We have proposed gate-all-around Silicon nanowire MOSFET (SNWFET) on bulk Si as an ultimate transistor. Well controlled processes are used to achieve gate length (LG) of sub-10nm and narrow nanowire widths. Excellent performance with reasonable VTH and short channel immunity are achieved owing to thin nanowire channel, self-aligned gate, and GAA structure. Transistor performance with gate length of...
In this paper, we present a cost-effective JFET integrated in 0.18μm RFCMOS process. The design is highly compatible with standard CMOS process, therefore can be easily scaled and implemented in advanced technology nodes. The design impact on Ron and Voff is further discussed, providing the insights and guidelines for JFET optimization. Besides the superior flicker noise (1/f noise) characteristics,...
The compact and low power logic circuit design for multi-pillar vertical MOSFETs has been proposed. The proposed design with the multi-pillar vertical MOSFETs is very practical for considering the load capacitance and resistance by changing the number of the silicon pillars flexibly for the desired channel width of series connected MOSFETs and their layout pattern.
This paper discusses the newly introduced vertically-stacked silicon nanowire gate-all-around field-effect-transistor technology and its advantages for higher density layout design. The vertical nanowire stacking technology allows very-high density arrangement of nanowire transistors with near-ideal characteristics, and opens the possibility for design optimization by adjusting the number of nanowire...
In this paper, we introduce the cylindrical coordinate based flicker noise model for Silicon NanoWire Field Effect Transistor (Si-NWFET) with Gate-All-Around (GAA) structure. For the accurate extraction of the volume trap density, Nt, with 1/f noise modeling, the parameters which represent the intrinsic channel properties are determined by rejecting the series resistance Rsd effect. Due to the random...
This paper explores the challenges facing the 22nm process generation and beyond. CMOS transistor architectures such as ultra-thin body, FinFET, and nanowire will be compared and contrasted. Mobility enhancements such as channel stress, alternative orientations, and exotic materials will be explored. Resistance challenges will be reviewed in relation to key process techniques such as silicidation,...
We applied partial conversion as initial silicidation to control the morphologies of Ni-Pt silicide, viz., the thickness, crystal grain, and Pt concentration of the Ni-Pt silicide. This partial conversion kept the thickness of Ni-Pt silicide constant regardless of the device pattern, i.e., by controlling silicidation with thermal diffusion. The key to partially converting Ni-Pt silicide was leaving...
The DC and AC characteristics of the multi-pillar vertical MOSFET's have been studied, considering the silicon pillar diameter thinning cases due to the process fluctuation. In order to suppress the pillar thinning influences, the Inter Contacts design has been proposed, which can realize the compact, high-speed, low-power, and stable circuits with the multi-pillar vertical MOSFET's.
Incorporation of platinum (Pt) into nickel silicide (NiSi) improves the reliability and thermal stability of electrodes in Si MOSFETs. Increasing the Pt content is desirable for further scaled CMOS, but incorporation of more Pt would tremendously increase the material cost. In addition, since Pt is one of the key materials for eco-technology such as catalyst for exhaust absorption and so on, reduction...
In this work, gate-all-around (GAA) poly-Si nano wire (NW) thin film transistors (TFTs) with record physical gate length of 30 nm and driving current >100 μA/μm are demonstrated. The cross section of the NW channel is as small as 35 nm × 8 nm. The tight GAA and NW structure enhances the gate potential control ability effectively, therefore, excellent short channel and narrow width behaviors can...
The difference in the number of contacts across different transistors and standard cells results in current variations across the channel. In this work, we present test structures to target this effect and characterize and quantify the impact on 45 nm SOI silicon. After comparing the impact of contact resistance between 65 nm and 45 nm silicon, we provide and analyze our 45 nm test structure results...
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