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In this paper we have demonstrated the 12 inch (300 mm) wafer level fabrication and characterization of a laminated CoZrTa-based magnetic thin film stack with excellent magnetic and electrical properties. Clear magnetic anisotropy with low coercivity (∼0.3 Oe) and high permeability (∼500) were achieved. High resistivity (∼92.8 μΩ·cm) was also obtained for a four-fold lamination stack. Adhesive properties...
A high-directivity microstrip-fed Yagi-Uda antenna has been developed for millimeter-wave applications. This work proposed antenna is built on a low-cost and low-loss multilayer organic substrate for flip chip ball grid array (FCBGA) package. The proposed antenna achieves both broadband and high gain characteristics, which meets the requirement of IEEE 802.1 lad standard. The four-element Yagi-Uda...
A ball grid array (BGA) is a type of surface-mount package used for integrated circuits. In more advanced technologies, solder balls may be used on both the PCB and the package. Also, in stacked multi-chip modules, solder balls are used to connect two packages. The process steps prior to the final BGA ball mount process are becoming increasingly complex, which will induce BGA pad surface oxidation...
On-chip RF loss management is a critical issue for the packaging of the silicon photonics ICs (Si-PIC) determining signal integrity of both devices and systems. In this paper, we present optimal condition of on-chip transmission lines (TLs) for Si-PIC based on SOI wafer. Optimal on-chip 3dB-loss length is studied and crosstalk is analyzed for the multichannel TLs. The 3dB length is calculated to be...
In comparison to GC-MS applications in semiconductor front end (wafer fabrication), this technique seems to have fewer applications in semiconductor back end (package assembly processes assessment. In this work, GC-MS is applied in a different analysis approach for cleaning efficiency assessment in one of the back end processes. This analysis approach is proposed, executed, assessed, improved and...
The objective of this paper is to investigate the molding process in MEMS wafer level packaging solution. In this approach we adopted conventional molding process to complete the MEMS capacitive sensor packaging in order to achieve cost-effective full wafer-level packaging solution. It is important to secure void free molding because any voids generated nearby the eutectic bonding area will impair...
Typical epoxy-based electronic packaging materials necessitate substantial inclusion of flame retardant additives in order to satisfy regulatory requirements regarding flammability, usually evaluated by the UL-94 flammability test. Conventional additives such as encapsulated red phosphorus may pose a reliability issue under high humidity environment due to its hygroscopic nature, leading to electrical...
This paper proposes an indirect AC-AC converter based on linear controller and analyzing the variations in input supply and load demands. The proposed converter has controlled by a three-phase switch to achieve the optimal AC frequency. The proposed converter has dramatically reduced the output voltage ripples and sustains the voltage stability when connected with different loads. As a result, the...
The exciting moments for cellular networks is the currently on-going deployment of fourth generation (4G) networks offering services to customers worldwide. The key asset for users and operators alike is the support 5G networks continue to receive towards improved communication systems. This paper addresses issues of integrated resource scheduling within cellular networks and proposing an improvement...
In the past few decades there have been many developments in the design methodology of DAC to meet the stringent performance requirements of their endless applications. These design strategies can be categorized into several classifications. Based on the literature review the history of the evolution, advantages and limitation of each method can be summarized. Such survey is of high essence to meet...
This paper presents the performance comparison of PV windows with the purpose of tracing the behavior of next-generation systems, which could favor architectonical integration. More in detail, a dye sensitized solar cell (DSSC) and blue and grey thin film silicon panels have been analyzed. The systems can be placed behind a window or behind a wall of glass blocks. The three generation systems are...
The aim of this paper is to draw a state-of-the-art related to the electric motors for grid connected integrated battery chargers in electric vehicle applications. The design process of this type of chargers consists to use the power electronics devices and the electric motor to charge the battery packs when the vehicle is plugged to grid. Actually, any standard has been established. So, this paper...
The Tubular Linear Induction Machine (TLIM) has acquired great relevance over the past years for industrial automated applications. For this purpose, the complete modeling, simulation and determination of the parameters of a TLIM is presented in this paper. In addition, the TLIM speed control for this specific application is here described. In order to verify the performances of the proposed system,...
This work presents a subthreshold operational amplifier with current subtractor adaptive biasing circuit designed using a formulated design methodology based on gm/ID method. A subthreshold operational amplifier is an operational amplifier that offers ultra-low power consumption. This is to replace conventional operational amplifiers in most IC by which the application are for RFID, WSN, IoT, and...
A row decoder circuit is required for the successful programming, reading, and erasing voltages of an electrically erasable programmable read only memory (EEPROM) implementation in low-power applications like radio frequency identification (RFID) tag. The row decoder has been implemented in 0.18 μm CMOS process. The designed row decoder can generate sixteen output signals, which is used in sense amplifier...
The socket is regarded as a testing interface. It can measure the performance of package and fix the signal path from ATE to DUT (Device under Test). With testing frequency getting higher and higher, it will cause SI (Signal Integrity) problem when testing. The signal can't transmit completely with high frequency because of the excessive loss. Therefore, to solve this problem, use de-embedding method...
Lithography is a key enabling technology for semiconductor devices and circuits. The CMOS scaling continues to drive lithography to sub-10 nanometers resolution. The challenges of advanced wafer level packaging (WLP) are very different from CMOS technology. Generally, advanced WLP process requires not only good critical dimension control and nearly 90 degree vertical resist profile, but also requires...
Key end user applications, such as Internet of Things (IoT), automotive, mobile internet and wearable devices, require smaller, denser and more complex packages with increased performance, all at a low power usage. Innovative front end technologies enabling transistor downscaling towards 10 nm pave the way for small pitch components with an increased I/O count, thus leading to a packaging technology...
“Cliff test” studies with thermosonic wirebond of 25μm copper (Cu) wire were done on integrated circuit pads having either 0.8μm or 3.0μm aluminum (Al) thickness to investigate the effect on intermetallic (IMC) formation and shear test results. One half of the pads had been probed, leaving relatively large and invasive probe marks, while the other pads were unprobed prior to wirebond. Manufacturing...
The introduction of Chip Scale Package (CSP) has become one of the key packaging solutions in the recent semiconductor industry. With the advantages of reducing the package size and stacking capability for higher interconnects, CSP's are continuously evolving into many different types of CSP's packages. One of the key innovative package solutions is the molded wafer level CSP (mWLCSP)1, 2 due to the...
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