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The article addresses a design procedure of low-power variable gain amplifier employing so-called bulk-driven transistors in 130 nm CMOS technology, working with the power supply voltage of only 600 mV. Mentioned approach represents rather unconventional and still quite uncharted design technique. Therefore, the research potential is tremendous. The paper describes the proposed amplifier along with...
Although switched-mode Electronic Loads (E-Loads) are commonly used in different applications, they are facing particular limitations especially for higher frequency purposes. While increasing the switching frequency in switched-mode E-Loads enables them to operate at high frequencies, simply rising the switching frequency might not be an efficient approach in terms of design issues, device limitations,...
This paper deals with the design of logic gating signal generator circuit implemented in Staircase modulation technique in order to eliminate Boolean simplification and making the computational process more handled assigning processing task to gate arrays. The control system implementation is described and its performance is evaluated through a 21-level half-bridge MMC based system simulation using...
There are mainly two kinds of DC power supply voltages such as 28V, 42V in small and medium power level satellites. A novel cascaded current fed DC/DC topology which can cover all these input voltages was proposed. The working principle of the cascaded topology which composed by a Buck converter cascaded with a current fed push-pull converter was analyzed. With a synchronous rectifier circuit, high...
A low drop-out (LDO) voltage regulator with high power supply rejection ratio (PSRR) and enhanced transient response is presented in this study. The proposed idea is to apply a replica circuit that injects current into the second stage of the error amplifier. The LDO is being fabricated in Magna Chips CMOS Technology. The regulated output voltage of the LDO is 1V with the power supply voltage of 1...
A single-inductor-cascaded-stage boost regulator topology is presented that time-multiplexes a single inductor using one-nFET-two-pFET power stage and a bias-gated Pulse-Frequency Modulation controller to achieve high conversion ratio. A test-chip in 130nm CMOS demonstrates 120× conversion using a single inductor while consuming 140nA bias current.
A dimmable and power-compensated AC direct LED driver with high efficiency for lighting applications is presented. A Source-Coupled Pair (SCP) is adopted to realize the soft self-commutating. There is no additional sensing or control circuitry, which lower the system power dissipation. A pulse-width modulation (PWM) dimming technique is applied in regulating the LED's brightness. Furthermore, the...
There are so many reasons for evolving from single gate to triple gate structures MOSFET. MOSFET works on the principle that by variation of the applied voltage at first current through the device enhances linearly but then it approaches saturation (fixed current). If we implement 3 gate terminals we can establish of flexible control over the amount of current. By variation of one gate voltage the...
In this paper, we present a resistive switching memristor cell for implementing universal logic gates. The cell has a weighted control input whose resistance is set based on a control signal that generalizes the operational regime from NAND to NOR functionality. We further show how threshold logic in the voltage-controlled resistive cell can be used to implement a XOR logic. Building on the same principle...
PACIFIC is a 64 channel mixed-signal ASIC designed for the readout of the Scintillating Fibre (SciFi) Tracker developed for the LHCb upgrade in 2018/19. The SciFi Tracker uses as active material 250 μm scintillating fibres, stacked in 6 layer mats and sensed by custom designed 128 channel silicon photomultiplier (SiPM) arrays. It will be comprised of 12 planes, each covering an area of 5×6 m2. PACIFIC...
This paper presents circuit modeling, design, simulation and analysis of noninverting buck boost converter. Closed loop simulation is carried out using PI and digital gates in voltage mode control technique using PSIM 8.0.7. The system can operate in buck, buck-boost or boost mode according to the condition of the supply voltage. Load and line regulations analysis is done and it is found to be 0.0125...
A fully integrated, reconfigurable step-up DC-DC switched-capacitor power supply solution for energy harvesting system is presented in this paper. A new series-parallel architecture of step-up switched-capacitor converter with Pulse Skip Modulation (PSM) is proposed. This converter generates a stable regulated output (1.2V) from an ultra-low input voltage of 0.3V–1.2V. The designed converter achieves...
A novel Dynamic Carrier-Storage IGBT (DCS-IGBT) is proposed. With Gate (hereinafter, G) and Control Gate (hereinafter, CG), two independent gates integrated in one trench area, CG can be applied with different bias to modulate the carrier-storage layer dynamically. When the device is on, positive bias on CG can raise the concentration of the carrier storage layer leading an increase of the current...
A pre-modulated step-up DC-DC converter with high-conductance switches is proposed in this paper. The modified switches used in the charge pump extend the gate-source voltage of PMOS power transistors and adjust the threshold voltage of NOMS ones based on body effect when the switches turn on, contributing to the increase of conductance. Pre-modulation technique works to maintain the output voltage...
Use of power gates for leakage power reduction comes at the expense of higher DC and AC load lines due to location of voltage regulator sense point before the power gate and choice reference voltage to guarantee minimum voltage across all power gate and load conditions. This paper proposes schemes to dynamically change both the sense voltage and the reference voltage to reduce AC & DC load lines...
Integrated gate-drivers for power MOSFETs require multiple supply voltages biasing internal circuitry or providing a high voltage ground to the high-side driver. This paper proposes a novel DC-DC converter architecture fulfilling these demands of modern gate-driver ASICs while increasing system efficiency. In the proposed concept a conventional single inductor DC-DC converter generating a low voltage...
An advanced gate drive unit for 1.2 kV IGBT modules has been developed. It includes two main features: limitation of the collector-emitter voltage slope and of the collector-emitter peak voltage. This is achieved through a feedback loop with a capacitive/resistive voltage divider coupled to the gate-emitter voltage of the IGBT. For the studied case a reduction of the switching losses of around 25%...
A high-voltage compliant, 65nm bulk-CMOS neural stimulator front-end is presented which can interface with a wide range of electrode impedances. With bulk-CMOS compatibility, the presented design can be easily integrated on the same silicon chip with other blocks needed for implantable bidirectional neural interfaces (e.g. high-density neural recording, DSP, memory, wireless interfaces). Measurements...
A low power flipped voltage follower (FVF) based output capacitor-less low-dropout (LDO) regulator, designed for the low power radio frequency identification (RFID) chips, has been proposed and simulated by using a standard 0.18 µm CMOS process in this paper. Utilizing the FVF structure and dynamic bias current technique, proposed LDO is able to achieve a fast transient response and the power supply...
High-speed PLL control voltage stabilization method is presented in the paper. Fully integrated modified PLL circuit is designed accordingly. Stabilization principle is based on compensation of the LPF MOSFET capacitor output voltage which is unstable due to gate oxide leakage currents. Stabilization is implemented by using analog latch circuit and holding correct VCO control voltage. Latched voltage...
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