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Detecting vulnerabilities in binary codes is one of the most difficult problems due to the lack of type information and symbols. We propose a novel tool to perform symbolic execution inside the routines of binary codes, providing easy static analysis for vulnerability detection. Compared with existing systems, our tool has four properties: first, it could work on binary codes without source codes,...
The MEMOCODE design contest for 2014 was centered around the emulation of the 1978 Taito video game Space Invaders. The challenge is to improve the speed of a cycle-accurate software emulator for the game. Contestants had a month toope improve the provided code, which already ran fairly well on the ARM-based Raspberry Pi platform. Entries were judged on how much faster their code ran and its quality...
LED test can be done in several stages of the manufacturing process of a device. Although ICTs can check the electrical parameters of LEDs, they do not always have extensions for chrominance and luminance measurements. This paper presents a test system for both colour and light intensity of LEDs, designed to communicate with a computer via USB. Test system has a graphical interface that allows operation...
This paper presents an extensive performance study of the implementation of Hardware Transactional Memory (HTM) in the Haswell generation of Intel x86 core processors. This study evaluates the strengths and weaknesses of this new architecture exploring several dimensions in the space of Transactional Memory (TM) application characteristics using the Eigenbench [1] and the CLOMP-TM [2] benchmarks....
Return-oriented programming is a kind of codereuse technique for attackers, which is very effective to bypass the DEP defense. However, the instruction snippet (we call it gadget) is often unprintable 1. This shortcoming can limit the ROP attack to be deployed to practice, since non-ASCII scanning can detect such ROP payload. In this paper, we present a novel method that only uses the printable gadgets,...
Complex Event Processing (CEP) is an emerging field in high performance computing paradigm where real time (low latency) computing capability is expected over big data processing (high throughput). Significant number of software architectures have been developed to improve the throughput while reduce the latency but maintaining of the both aspects reaches the limits of the software platforms. This...
In order to dynamicly monitor and manage the working state of space science experiment payloads, the large volume of science data should be performed for real-time transmission. According to this requirement, the paper proposes a design scheme of main information network based on Ethernet. A microprocessor TMS320F2812 and the Ethernet interface chip KSZ8851 are applied to set up the Ethernet communication...
Monitoring applications at run-time and evaluating the recorded statistical data of the underlying micro architecture is one of the key aspects required by many hardware architects and system designers as well as high-performance software developers. To fulfill this requirement, most modern CPUs for High Performance Computing have been equipped with Performance Monitoring Units (PMU) including a set...
Integrating FPGAs with a general purpose computer remains difficult, but recent efforts have resulted in open frameworks that offer a software API and hardware interface to allow easier integration. However, such systems only support static FPGA designs. With the addition of partial reconfiguration (PR) support, such frameworks can enable more effective use of FPGAs. Now, designers can incorporate...
Upcoming telecommunication networks are expected to lower energy requirements of current infrastructures, especially at the network edge. That necessarily entails cutting off energy wasted when devices are active, yet idle, just to maintain their presence on the network. To this purpose, the concept of delegating network activity has been introduced to allow devices to enter low power states without...
Priority queues are abstract data structures where each element is associated with a priority, and the highest priority element is always retrieved first from the queue. The data structure is widely used within databases, including the last stage of a merge-sort, forecasting read-ahead I/O to stream data for the merge-sort, and replacement selection sort. Typical software implementations use a balanced...
A high-performance interconnection between a host processor and FPGA accelerators is in much demand. Among various interconnection methods, a PCIe bus is an attractive choice for loosely coupled accelerators. Because there is no standard host-FPGA communication library, FPGA developers have to write significant amounts of PCIe related code at both the FPGA side and the host processor side. A high-performance...
While the resilience of software-only code obfuscation remains unclear and ultimately depends only on available resources and patience of the attacker, hardware-based software protection approaches can provide a much higher level of protection against program analysis. Almost no systematic research has been done on the interplay between hardware and software based protection mechanism. In this paper,...
In this paper, an application-specific instruction-set processor (ASIP) implementation for interpolation operation for high efficiency video coding (HEVC) decoders is proposed. HEVC is a new video compression standard that has higher compression efficiency than the previous ones. The proposed ASIP is implemented on the XRC_D2MR processor by augmenting the instruction set architecture in Xtensa Tensilica...
In cloud computing, hypervisor is the all-powerful software running in the highest privilege layer, thus attackers who compromise a hypervisor may jeopardize the whole cloud, especially cause memory corruption of any sensitive workloads within the cloud. In this paper, we propose a novel architecture and approach to provide memory protection from an untrusted hypervisor on current x86 platforms. Unlike...
With the rapid development of software technology and open source projects, software industry becomes more and more threatened by software piracy. As an excellent detection technique of software piracy, software birthmark, which can describe the unique characteristic of a program, has obtained more and more attention. In this paper, we propose a software birthmark called SCDG-DDGB (System Call Dependence...
Common way for IP-Core standalone verification assumes UVM based environments and tests development. At the same time, IP-core integration verification at the SoC level and hardware-software co-verification as a whole, requires development of the code running on the embedded CPU (usually written on C/C++). When C/C++ tests and software are developed it is desirable to reuse IP-Core standalone level...
In using ontology to support requirements engi-neering, quality of elicited requirements depends on quality of requirements ontology, so a rule-based verification method of the correctness of requirements ontology has been proposed. However, in recent evaluation experiments, users of the method (ontology verifiers) described only a few new rules based on rule grammars and rule examples. That led to...
This paper describes in detail the robot platform used in a rehabilitation program for children with Traumatic Brain Injury (TBI) under a project to compare a rehabilitation program through robotics (1) with a conventional rehabilitation program directed to parents (2) and a control group where no specific intervention is done (3). As LEGO ® has been demonstrated as a useful robotic tool able to enhance...
A 64-bit RISC processor is designed for large applications that need large memory address. Due to the restriction of the instruction fixed length, loading a 64-bit address needs a number of instructions, leading to a penalty both of memory performance and memory consumption. This paper describes an address computation method based on hardware and software co-design. In our extended MIPS processor...
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