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This paper presents a methodology to model and analyze the functional behavior of logic circuits under timing variations. In the framework, first a Time Accurate Model (TAM) of the circuit is constructed. The TAM represents the behavior of the circuit in the functional domain under a discrete time model. Afterwards, Variation Logic is inserted to apply the timing variations. Moreover, the circuit...
Noncoherent UWB receivers promise low power consumption and low processing complexity but their peak data rate is limited by the delay spread of the multipath radio channel. A recently proposed multichannel autocorrelation receiver (AcR) can break this rate limit due to its multicarrier signal demodulation capability. In this paper, the hardware implementation of this receiver architecture is addressed...
The introduction of communication systems to power system controllers have brought in another layer of complexity in their design and operation. In this paper a Plug-in Hybrid Electric Vehicle (PHEV) charging facility is studied. A linearized model of the facility is built including both the dc/dc and dc/ac converters of the Distributed Energy Resources (DER). In addition, a control strategy that...
Acoustic feedback is a serious problem in hearing aids. The feedback can result in whistling sound and make people who have severe hearing loss feel terrible. Traditional LMS and normalized LMS algorithm have been studied before, but these algorithms do not provide satisfactory performance for reducing feedback oscillation in hearing aids. So a band-limited NLMS algorithm is proposed. In order to...
As CMOS technology is scaled down more aggressively; the reliability mechanism (or aging effect) caused by progressive gate oxide breakdown (also called time dependent dielectric breakdown (TDDB)) has become a major reliability concern. The oxide breakdown is categorized into hard breakdown (HBD) and soft breakdown (SBD). With the present of HBD and SBD, it is difficult to control the ON current of...
Input/Output Buffer Information Specification (IBIS) behavioral models are widely used for circuit-level signal integrity (SI) analysis due to its fast simulation speed and good accuracy. This work presents a tool to generate models of circuits specified by IBIS models. The model generation tool estimates poles, rise time and fall time of a circuit specified by IBIS models. The method consists of...
A design method for an over-lOG-b/s buffer circuit for generating precise delay is proposed. A simple small-signal equivalent circuit model is introduced to investigate the delay characteristics of a current mode logic (CML) buffer circuit with load resistances. By setting the transconductance generator gm and output resistance in a MOSFET model as a function of drain current, the design equations...
The synchronous programming model is perfect for modeling, simulation, verification and implementation of reactive systems. While this paradigm can be directly implemented as hardware circuits, multithreaded software implementations are typically based on asynchronous threads. For this reason, an efficient multithreaded software implementation of a synchronous program requires a so-called desynchronization...
This paper presents two fully synthesizable and emulation friendly delay cell designs that the authors have successfully implemented in a real emulation environment. Due to the analog nature of delay logics, none of the commercial emulators were able to support the actual delay behavior. Thus, manual additions of register were needed for each customized scenario. The effort required is huge and highly...
Carbon Nanotube (CNT) has become the promising candidate for replacing the traditional Copper (Cu) based interconnect systems in future technology nodes. This paper presents an analytical model for timing and crosstalk in the CNT based nano-interconnect systems. The proposed model is compared with SPICE and it is found that the proposed model is 100% accurate with respect to SPICE and in an average...
A systematic method is proposed to address modeling challenges in accurate chip level leakage prediction, namely a precise total leakage width count method, a simple model to quantify leakage uplift caused by systematic across-chip variation, and a consistent model to capture 3-sigma leakage and leakage spread at fixed performance.
In this work, simple explicit delay and rise time expressions for uniformly distributed RLC on-chip interconnect line are derived based on Elmore's approximations. Here, an n-cell RLC ladder network with capacitive load is used. Transfer function for the n-cell RLC ladder network is obtained by using the transmission line parameter matrix for each cell. In order to deduce the transfer function, the...
This paper presents a novel and accurate analytical approach for the efficient computation of the transient response and 50% delay of on-chip RLCG interconnect lines with a capacitive load. The proposed model is based on the two port representation of the transmission line. The simulation results are obtained by using the proposed model and found to be at good agreement with that of the SPICE simulation...
This paper presents a correction technique of microwave/digital signal integrity with a negative group delay (NGD) active circuit potentially integrable. A theoretical approach illustrating the functioning of the NGD topology is established. The method for synthesizing the NGD circuit in function of the signal degradation parameters is developed. The relevance of the technique is verified with a proof...
To characterize statistical moments of cell delays and slopes, the standard method is Monte Carlo (MC) method. However, this method suffers from very high computational cost. In this paper, we propose a technique to quickly and accurately estimate Standard Deviation (SD) of standard cell delays and slopes. The proposed technique is based on the identification, performed with a reduced set of MC simulations,...
Minimizing circuit AC delay variations while maintaining power/performance is key for achieving high yielding products. The present work discusses an analytic model based approach for aligning the fundamental-FET electrical control and circuit-speed variability applied towards product screening. Such a model is proven to be effective in a manufacturing environment for predicting delay variation, and...
In this paper state space and circuit realizations are presented for 2D Reverse-Lattice based filters. The proposed state space realizations are based on the corresponding circuit implementation. For the state space realization the 2D Cyclic model, having minimal dimension and delay elements, is used. Two low-order representative examples are presented to illustrate the proposed results using, 2D...
Bias Temperature Instability (BTI) becomes one of the most important reliability issues for nanometer process devices. We focus on aging degradation by BTI because it is known as one of the dominant factor that determines life time of circuits. In this paper, we show circuit delay degradation characteristic of BTI using the circuit simulation. The delay increase 15% after 10 years stress.
Paths that cannot be sensitized during functional operation do not need to be optimized for speed, and their delays may be higher than the clock period. This paper uses functional broadside tests for path delay faults in order to avoid overtesting due to the detection of faults that are associated with such paths. To ensure that as many small delay defects as possible will be detected, the paper considers...
Resistive open fault (ROF) represents common manufacturing defects causing extra delays and reliability risks in affected circuits. ROF behavior is sensitive to the supply voltage and the resistance of open (RO). Modeling this fault behavior and detectability with the supply voltage helps in distinguishing between faults as well as testing of multi-voltage designs. While previous ROF models did not...
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