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High-voltage power metering systems based on electronic instrument transformers (EITs) have some advantages compared to the conventional ones. This paper describes an unique calibration method and device for the power metering system. High accuracy with the calibration method can be achieved. The estimated relative uncertainty of the device is about 200×10−6 in magnitude and less than 110 µrad in...
This paper presents a fast response digitally controlled full bridge converter in parallel operation. The digital controlled circuit has some problem. One of the main problems is the delay time. The delay time includes the conversion time of A-D converter and processing time of digital controller. It exerts a bad influence on the dynamic characteristic. In the proposed method, the sample timing for...
We reconsider guarded evaluation as a means to reduce FPGA dynamic power consumption. We augment and evaluate guarded evaluation as proposed in [1] after different stages of the FPGA CAD flow. Guarding later in the flow provides more feedback to the algorithm and yields a more effective cost-benefit analysis of newly added signals. Numerical results show that guarding later in the flow yields slightly...
In this work, we are about to introduce a high performance NetFPGA based network measurement system, called Rnetprobe that implements a dual, multi-layer timestamping method for QoS analysis. The multi-layer timestamping idea came from the demand to perform end-to-end active measurements that enable improved cross-layer analysis to evaluate QoS for time sensitive services. Accordingly, for each captured...
This paper describes a very simple Digital Pulse Width Modulator (DPWM), with under 100 picoseconds resolution capability in low-cost field-programmable gate arrays (FPGA). The DPWM implementation is based on internal carry chains and internal logic resources which are present in most FPGA families. The proposed approach does not require manual routing or placement, consumes few hardware resources,...
The {2^n + 1, 2^n - 1, 2^(2n+1) - 3, 2^(2n) - 2} moduli set and the respective reverse converter have been recently proposed for supporting Residue Number Systems (RNSs). The reverse converter originally proposed was based on the Chinese Remainder Theorems (CRTs), in particular the commonly called new CRTs, and requires at the end a 6nbit carry propagate adder to compute the binary value. In this...
This paper presents an easy to design Physically Unclonable Function (PUF). The proposed PUF implementation is a loop composed of identical and controllable delay chains which are serially assembled in a loop to create a single ring oscillator. The frequency discrepancies resulting from the oscillator driven by complementary combinations of the delay chains allows to characterize one device. The...
Large multiplication is widely used in modern cryptography systems, multimedia and signal processing applications. This paper presents three pipelined large multiplier (PLM) design methods that use specialized multiplier logic provided in modern FPGA platforms. The presented design methods provide efficient usage of symmetric multiplier resources. Also, they can be used to map a large multiplier even...
This paper presents a novel approach for the design of ring oscillators in a combined true random number generator (TRNG). We propose using delay elements made on carry4 primitives instead of series of inverters or latches in ring oscillators, which enables the construction of many high frequency ring oscillators with different nominal frequencies in the same field programmable gate array (FPGA)....
The purpose of this paper is to present a digitally controlled dc-dc converter with a novel peak current injected technique. In the proposed method, the peak current is able to be detected by using a voltage controlled oscillator (VCO) which is very low cost and the simple delay circuit implemented by the a field programmable gate array (FPGA). As a result, it is confirmed the main switch is turned...
We present experimental results for performance of the 2D hypermesh NoC topology, realized with the Altera Family of FPGAs. Hypermeshes are based on the concept of hypergraphs, which consist of a set of nodes and a set of hyper-edges, where the hyper-edges represent low-latency distributed switches. In a 2D hypermesh, the nodes in each row or column are members of a hyperedge, where packets can traverse...
A new Physically Unclonable Function (PUF) variant was developed on an FPGA, and its quality evaluated. It is conceptually similar to PUFs developed using standard SRAM cells, except it utilizes general FPGA reconfigurable fabric, which offers several advantages. Comparison between our approach and other PUF designs indicates that our design is competitive in terms of repeatability within a given...
This work presents a synthesis framework that generates a formally verifiable RTL from a high level language. We develop an estimation model for area, delay and power metrics of arithmetic components for Xilinx Spartan 3 FPGA family. Our estimation model works 300 times faster than Xilinx's toolchain with an average error of 6.57\% for delay and 3.76\% for area estimations. Our framework extracts...
In order to accelerate logic simulation, it is highly beneficial to simulate the circuit design on FPGA hardware. This is often referred to as emulation, and we use the terms simulation and emulation interchangeably in this paper. However, limited hardware on FPGAs prevents large designs from being implemented on a single FPGA. Hence there is a need to partition the design and simulate it on a multi-FPGA...
This paper presents a new digital peak current mode dc-dc converter using a FPGA delay circuit and a simple A-D converter. The peak current detection circuit is only composed of RC integrator and field programmable gate array (FPGA) delay circuit. The sampling point of detected current is changed by the feedback value of output voltage. The RC integrator is performed as the A-D converter for the current...
Time-Correlated Single Photon Counting (TCSPC) can provide not only the time information of a photon, but also the photon density information. Based on the conclusion of usual time interval measuring methods, this paper chooses the scheme of Time-to-Digital Converter (TDC) based on delay line structure, meeting the TCSPC system's requirement for high timing resolution. This TDC contains two delay...
The SRAM-based FPGA, due to their high performance, has become a popular choice in today's electronic systems and are used in large number of applications. But in radiation harsh environment these FPGAs require some additional mechanism to cope up with soft errors. Modern FPGAs are built in 28nm technologies, where even combinational circuits are substantially vulnerable to soft errors. Such designs...
Recently, forgery and counterfeiting of semiconductor products have become one of the most serious problems. These problems not only cause money damages, but also have the risk related to the safety of the life. Therefore, techniques to prevent forgery by using random characteristic patterns that are difficult to control artificially have attracted attention. The physical unclonable function (PUF)...
This paper describes a design for a variable fractional delay (VFD) FIR filter implemented on reconfigurable hardware. Fractionally delayed signals are required for several audio-based applications, including echo cancellation and musical signal analysis. Traditionally, VFD FIR filters are implemented using a complex, fixed structure based upon the order of the filter. This fixed structure restricts...
Exploiting computational precision can improve performance significantly without losing accuracy in many applications. To enable this, we propose an innovative arithmetic logic unit (ALU) architecture that supports true dynamic precision operations on the fly. The proposed architecture targets both fixed-point and floating-point ALUs, but in this paper we focus mainly on the precision-controlling...
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