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Subthreshold voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. This is beneficial in embedded applications that must run off of batteries and scavenged energy. Subthreshold operation has been proven to be very effective by several successful prototypes in the recent years, yet there is no fast and effective way for...
In this work, a new design approach in implementing low-energy, high-performance 64-bit adder using dynamic feedthrough logic (DFTL) is introduced and analyzed. Design issues of using DFTL in several logic depth are analyzed in order to achieve the best optimal balance between performance and power consumption. A ldquotiming windowrdquo technique is also proposed to reduce the amount of excessive...
Motivated by the unwillingness to accept the worst-case timing constraint that synchronous logic imposes, and additionally motivated by finding a supply voltage scaling scheme for datapath circuits that is unconstrained by timing errors in memory elements, the authors have built an asynchronous datapath that is embedded seamlessly into a synchronous register file. This paper will show that not only...
To maximize the potential of three-dimensional integrated circuit architectures, 3D CAD tools must be developed that are on-par with their 2D counterparts. In this paper, we present a statistical static timing analysis (SSTA) engine designed to deal with both the uncorrelated and correlated variations in 3D FPGAs. We consider the effects of intra-die and inter-die variation. Using the 3D physical...
Signal control based on bus priority is an important and economical way to implement the measures of bus priority. Among many kinds of methods of signal timing, this paper chooses the WEBSTER method. The bus priority signal timing program is based on the minimum of the total delay of the passengers, which is regarded as an optimal aim of cycle and green time. Compared with the average vehicle delay...
System-level software modeling and simulation have become important techniques for real-time embedded system early design space exploration. However, the timing accuracy issues have not been solved well in current methods, which produce unrealistic results or large simulation overheads. In this paper, we propose a mixed timing modeling and simulation approach to decouple conventionally interdependent...
As technology scales, leakage power shares a dominant part in the total power dissipation of the chip and reaches up to 50% or even higher at elevated temperatures in 45 nm technology. Leakage power dissipation is especially problematic for FPGAs due to their reconfigurable nature and large number of inactive resources. Body biasing is an efficient technique to reduce leakage current which has been...
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedded applications that have a high degree of task-level parallelism among computational kernels. The test chip was fabricated in 65nm CMOS consisting of 164 simple small programmable cores, three dedicated-purpose accelerators...
Wave pipelining has gained attention for NoC interconnect by its promise of high bandwidth using simple circuits. Reliability issues must be addressed before wave pipelining can be used in practice; so, we develop a statistical model of dynamic timing uncertainty. We show that it is important to distinguish between static and dynamic sources of timing uncertainty, because source-synchronous wave pipelining...
With the advent of networks-on-chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distribution. Recently proposed schemes agree on a source synchronous design style with some form of ping-pong buffering to counter timing and metastability concerns. However, the integration issues of such synchronizers in a NoC...
As a basic block of a multi-switching-and-processing system, fast and fair arbiters are critical to the efficiency of multi-core computing units, high-speed crossbar switches and routers, which are the key to the performance of on-chip networking/computing in a SoC and NoC. In this paper, a High-Speed and decentralized round-robin arbiter (HDRA) is presented. Unlike the conventional round-robin arbiters,...
As Globally Asynchronous Locally Synchronous (GALS) systems are becoming preponderant in complex SoC and NoC, we present the design and implementation of a new GALS adapter to be used in ANoC, an asynchronous NoC architecture. The proposed GALS adapter is a complete IP integration module, including a new FIFO based design using a Johnson-encoding principle for timing domains interfacing, and a local...
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing self-timed combinational logic is complex and expensive. This paper presents a novel method for synthesising indicating implementations of arbitrary encoded function blocks. The synthesis method reduces the cost of the implementations by distributing indication between the individual outputs...
Asynchronous circuit design can result in substantial benefits of reduced power, improved performance, and high modularity. However,asynchronous design styles are largely incompatible with clocked CAD,which has prevented wide-scale adoption. The key incompatibility istiming. Thus most commercial work relies on custom CAD or untimeddelay-insensitive design methodologies. This paper proposes a newmethodology,...
We present a heuristic based approach towards analyzing and optimizing the throughput of asynchronous pipelined circuits. Optimization allows specification of the target throughput. A variety of handshaking protocols and implementations are supported through a library approach.Timing arcs specified for library cells serve as a basis for throughput analysis. The algorithms described in the paper are...
In this paper we show results of a test campaign, designed to investigate the stability of GPS receiver clocks locked to an external frequency source. Two types of geodetic receivers and one timing receiver have been compared. The receivers were operated in pairs in zero and short baseline setups with common reference frequency. Care was taken to minimize environmental effects. The observation data...
In high-frequency microprocessor design, placement plays a significantly different role from that in large ASICs. Not only does it have to find a good global placement solution, placement needs tighter interaction with physical optimizations to improve every picosecond possible. This paper will introduce practical placement techniques that integrate buffering and gate sizing to maximize timing improvement...
The long term evolution (LTE) of 3GPP radio-access technology aims to develop a framework towards a high-data-rate, low-latency and packet-optimized radio access technology: Evolved Universal Terrestrial Radio Access Networks (E-UTRAN). However, low terminal transmission power, short TTI length and long HARQ RTT give a critical problem on LTE TDD UL performance in a coverage-limited scenario. To solve...
In this paper, a new symbol timing detection scheme robust to carrier frequency offset is proposed for time domain synchronous (TDS) OFDM systems. The proposed method computes the sliding correlation from both the differential received signal and the differential PN sequence. Rapid symbol timing detection can be obtained based on the correlation peaks. As differential operation is adopted before sliding...
Low-cost FPGAs have comparable number of configurable logic blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. This leads to the difficulty for CAD tools to successfully and optimally map a circuit into these devices. Instead of switching to resource-rich FPGAs, the designers could employ depopulation based clustering technique which underuses CLBs, hence improves...
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