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This paper deals with the design and analysis of 1Kb Static Random Access Memory (SRAM) at 180nm, focusing on optimizing power and delay. The entire SRAM can be divided into 4 blocks with each block having equal capacity of 256b. The key of low power operation in the SRAM is to reduce the wordline capacitance. The sense amplifier is placed below the column decoder circuit. Here only one sense amplifier...
In this paper, we present a method for creating LDPC codes which are specifically designed to be hardware friendly. Our method involves constraining the cyclic shift values in the base H-matrix to reduce the complexity of the cyclic shift hardware. We show that the decoder hardware implementation for these codes has higher throughput and lower power consumption than decoders designed for traditional...
The design of random media access control (MAC) renews great attention for emerging challenged wireless environments where the propagation delay is long and varying, such as satellite or underwater acoustic sensor networks. In these environments, the existing MAC solutions based on slotted transmissions, carrier sensing, or channel reservation by control packets are no longer favorable or even feasible...
Access points (APs) of wireless LANs (WLANs), always powered on and ready to serve mobile nodes, consume a large amount of power in total, but are idle during much of the time. Previous protocol-based sleep-wakeup scheduling schemes partially solve this problem, but the large wakeup delay remains a problem. Aiming at realizing Radio-On-Demand WLANs, in this paper, we suggest using an additional wakeup...
When the video streams are transmitted over the unreliable networks, forward error correction (FEC) codes are usually used to protect them. Reed-Solomon codes are block-based FEC codes. On one hand, enlarging the block size can enhance the performance of the Reed-Solomon codes. On the other hand, large Reed-Solomon block size leads to long delay which is not tolerable for real-time video applications...
This paper describes the optimization of VP6 decoder for the MIPS based architectures. Programming languages C and inline assembler for the MIPS32 architecture were used. VP6 decoder with the main features is described, as well as MIPS processor and opportunities it offers. Profiling was performed for two data sets, and on the basis of these results optimization was performed using the vectorization...
This paper describes a control scheme for a 32×32bit 4-read, 2-write register file operating in 1.25GHz with TSMC 65nm LP (low-power) process. Signals from the timing control module can tolerate short clock pulse, which ensures that the register file can work well on high clock frequency. Due to the fact that the delay of the word-line driver in this design is easy to match, a dummy driver as well...
In this paper, the energy efficiency of cooperative ARQ transmission in Amplify-and-Forward (AF) relay networks is discussed. The average total energy consumed per bit for cooperative ARQ under Quality of Service (QoS) constraints is formulated. With numerical method, the objective is optimized over the transmission data rate, the transmit power of the source and the relay, given fixed maximum retransmission...
We introduce a low-complexity error-resilient perceptual haptic data reduction scheme addressing network packet losses. As shown in previous works, haptic packet losses highly impair telemanipulation systems displaying haptic artifacts and causing instabilities. Inspired by a previous error-resilient haptic data reduction approach, we propose a decreased-complexity binary tree scheme that aims to...
A sequential code such as an arithmetic code is a code that determines a prefix of the codeword from a prefix of the source sequence. The reciprocal of the time period in which the transmitter can send a single code symbol is called the transmission velocity. Since, at every moment, the restored length cannot be longer than the source length, the decoding rate is one at most. In this manuscript, we...
Recently, several papers have been concentrating on reducing the decoding complexity of high-rate space-time codes. While the research has led to some impressive reductions in decoding complexity, the geometric methods so far used appear to have faced some fundamental limits. In this paper, we study what happens if we let go of the assumption of full diversity and study the possibility of reducing...
During video streaming over packet-erasure network, packets may lose due to network congestion. Since video packets have different significance and validity for decoding, the streaming system is expected to transmit the most critical packets when congestion occurs. In this paper, a packet criticality model is proposed and then a video transmission framework based on this model is presented. The criticality...
Aiming at the problems of the falling decoded video quality of H.264/SVC (Scalable Video Coding) in the error prone transmission network, this paper proposes real-time feedback-based interactive error control methods suitable for low bit rate transmission. These methods make full use of the inter-layer prediction of spatial layers, improves the conventional feedback-based intra macro block (MB) update...
This paper aims to reduce the amount of prebuffering required to ensure a maximum video continuity in streaming. Current approaches do this by slowing the playout frame rate of the decoder, this is known as adaptive media playout (AMP). However, doing this introduces playout distortion to the viewers as the video is played slower than its natural playout rate. We approach this by proposing a frame...
Any physical channel of communication offers two potential reasons why its capacity (the number of bits it can transmit in a unit of time) might be unbounded: (1) (Uncountably) infinitely many choices of signal strength at any given instant of time, and (2) (Uncountably) infinitely many instances of time at which signals may be sent. However channel noise cancels out the potential unboundedness of...
An enhanced bandwidth extension scheme is introduced in this paper for wideband speech coding using ADPCM. The coded lower band signal plus small side information (some parameters) are transmitted instead of the whole band. In the decoder both frequency parts are reconstructed from the coded signal and the received parameters. In the proposed method, the high frequency part is derived from the excitation...
This paper presents the 10 Gb/s Ethernet Phy Forward Error Correction (FEC) sub-layer novel VLSI structure with the following 2 ideas: one is the frame boundary detecting methodology and the other is the fast frame synchronous structure. The first method increases the frame synchronizing speed by fully optimizing the candidate start position shift algorithm to accelerate the frame synchronization...
A comma detection and word alignment circuit is proposed for a 6.25-Gb/s SerDes. In order to achieve a high speed, a new architecture of combined parallel and pipelined is employed. Based on the proposed structure, a high speed comma detector is implemented using 0.18im CMOS technology. Post simulation result indicates that the circuit can operates up to 770MHz with a power consumption of 10.8 mW...
Joint detection in the uplink of a cellular network involving several non-colocated base stations is a promising means to turn inter-cell interference into useful signal energy and hence dramatically increase spectral efficiency of reuse one networks. To maximize the benefits of the new degrees of freedom that come with base station cooperation, cluster centric schedulers need to be aware of the interference...
In the radio channel, compression is used for transmission of real-time analog video signal and compressed bits can usually be transmitted at a non-constant rate. But standard video can be displayed on TV at a constant rate. It is difficult to decode the intermittent compressed data for real-time video display. In order to solve the problem which rate of video decoding and compressed bits in the radio...
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