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Content Centric Networking (CCN) Architecture has been suggested to overcome weaknesses of current Internet architecture. This architecture is based on the concept of decoupling data from location and retrieving contents by name instead of location. Transport layer protocol i.e. CCNx has been proposed for use with CCN. CCNx performs longest prefix match between requested content name and entries stored...
Space Wire is a standard of on-board networks for satellites promoted by the ESA. As the ESA plans to use Space Wire as the sole network for both critical and non-critical traffics, network designers need tools to check that all the critical messages meet their deadlines. We previously proposed two such tools to compute an upper-bound on the worst-case end-to-end delay of a packet traversing a Space...
A technique, based on the residue number system (RNS) with diminished-1 encoded channel, has being used for implementing a finite impulse response (FIR) digital filter. The proposed RNS architecture of the filter consists of three main blocks: forward and reverse converter and arithmetic processor for each channel. Architecture for residue to binary (reverse) convertor with diminished-1 encoded channel...
Rectangular Mesh is the most commonly used topology in the field of Network-on-Chip (NoC) due to its high regularity, symmetry and scalability. In this paper, we examine Honeycomb topology as another candidate for NoC architectures. Based on the simulations of Mesh and Honeycomb routers and network, we compare these two topologies in terms of power consumption, area cost and communication delay. Results...
Exploiting computational precision can improve performance significantly without losing accuracy in many applications. To enable this, we propose an innovative arithmetic logic unit (ALU) architecture that supports true dynamic precision operations on the fly. The proposed architecture targets both fixed-point and floating-point ALUs, but in this paper we focus mainly on the precision-controlling...
In the CMOS technologies below 65 nm the wire delay dominates the gate delay. 3D IC design is one solution to deal with this problem. We propose in this work to implement two different MPSOC architectures based on Mesh and Butterfly NoC topologies. We use the 3D IC technology from the Tezzaron Company. Thanks to its symmetry, the mesh based NoC architecture is easier to implement compared to the other...
How to provide quality of service (QoS) guarantees in routing and switching systems has become one of the key research topics in the areas of routing and switching technologies. Differentiated services architecture (DiffServ) is known as a promising way for supporting QoS in a high-speed backbone network scenario. However, the measurement indexes for realtime multimedia traffic, which plays very important...
Vehicular network is different from wired network due to its network environment changes rapidly. The connection lifetime between vehicles is usually short because vehicles move in high speeds. Hence, deploy peer-to-peer (p2p) applications over vehicular network is a challenging research issue. There are many problems confronted in p2p file sharing, e.g. how to search files effectively, how to share...
Scale-out datacenters mandate high per-server throughput to get the maximum benefit from the large TCO investment. Emerging applications (e.g., data serving and web search) that run in these datacenters operate on vast datasets that are not accommodated by on-die caches of existing server chips. Large caches reduce the die area available for cores and lower performance through long access latency...
Data replication is a well-known strategy to achieve the availability, scalability and performance improvement goals in the data management world. However, the cost of maintaining several database replicas always strongly consistent is very high. The CAP theorem shows that a shared-data system can choose at most two out of three properties: consistency, availability, and tolerance to partitions....
With the advances of e-Science, scientific workflow has become an important tool for researchers to explore scientific discoveries. Although several scientific workflow management systems (SWFMSs) have been developed, their support of exception handling is still limited. In this paper, we introduce our approach of exception handling in the VIEW scientific workflow management system. We propose an...
In the near future, embedded systems containing hundreds of processing elements running multiple concurrent applications will become a reality. The heterogeneous multicluster architecture enables to cope with the challenging hardware/software requirements presented by such systems. This paper shows principles and optimization of multicluster dimensioning aiming at an appropriate distribution of applications...
The Protein Processor Associative Memory (PPAM) is a novel hardware architecture for a distributed, decentralised bidirectional, hetero-associative memory, that can adapt online to changes in the training data. The PPAM is fundamentally different from traditional processing methods that tend to use arithmetic operations to perform computation. In this paper, we evaluate the fault tolerant properties...
As the number of processing elements in the future Networks on Chip (NoC) increases from multi-cores to many-cores, the role of the interconnection communications becomes more critical. The number of cores on a System on Chip (SoC) will reach thousands in the near future as predicted by the International Technology Roadmap for Semiconductors (ITRS). Currently, NoC interconnections are mostly implemented...
Management of household appliances and the services have been complicated by increasing of network devices recently. Therefore, Home Gateway (HGW) which manages them intensively has been expected as new consumer electronics. However, HGW has not been popular in our life because the installation cost of HGW is expensive compared with the benefits of services. In this study, we propose new home network...
We Propose a 2K/4K/8K point FFT (Fast Fourier Transform) for OFDM (Orthogonal Frequency Division Multiplexing) of DVB-H (Digital Video Broadcast Terrestrial) Receiver. The proposed FFT architecture utilizes cascaded radix-4 single path feedback (SDF) structure based on the Radix-2/Radix-4 FFT algorithm.[11] We use block floating point scaling technique in order to increase SQNR. The 2K/8K FFT consists...
Multi-stage buffered Clos-network switches suffer from out-of-sequence packet forwarding. This paper proposes a three-stage memory memory memory (MMM) Clos-network switch, called the MCS switch, which provides in-sequence packet forwarding while maintaining high throughput. The proposed MCS switch adopts the oldest-cell-first selection for arbitrations at the first and second stages and an iterative...
This paper describes the architecture (circuit design) and principles of operation of sigma-delta Sigma-Delta time-to-digital converters (TDC) for high-speed I/O interface circuit test applications, they offer good accuracy with short test times. In particular, we describe multi-bit TDC architectures for fast testing. However, mismatches among delay cells in delay lines degrade the linearity...
This paper is focused on the research of instruction scheduling technology for clustered VLIW architecture. A novel scheduling technology is presented in this work, which exploits the tradeoff between the balancing of distribution of instructions amongst clusters and reduction of the amount of inter-cluster data communications, and guides the cluster assign and cycle schedule of instructions by estimating...
In this paper, we present the use of a system aimed at improving the productivity of equipment, piloted at an Intel production facility for 300mm 45nm high volume manufacturing. We show that true toolset utilizations may be significantly lower than what is recorded, owing to various process and tool-related delays that occur during the tool ‘busy’ or ‘running’ state. We then demonstrate through a...
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