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In a circuit with enhanced-scan, any two-pattern test can be applied to detect delay faults. However, the tests may deviate substantially from functional operation conditions, and result in overtesting. Functional broadside tests create functional operation conditions during their functional clock cycles by using reachable states as scan-in states. To maintain a proximity to functional operation conditions...
The counterfeiting of integrated circuits (ICs) has been on the rise over the past decade, impacting the security and reliability of electronic systems. Reports show that recovered ICs contribute to about 80% of all counterfeit ICs in the market today. Such ICs are recovered from scrapped boards of used devices. Identification of such counterfeit ICs is a great challenge since these ICs have an identical...
In this work, we are about to introduce a high performance NetFPGA based network measurement system, called Rnetprobe that implements a dual, multi-layer timestamping method for QoS analysis. The multi-layer timestamping idea came from the demand to perform end-to-end active measurements that enable improved cross-layer analysis to evaluate QoS for time sensitive services. Accordingly, for each captured...
High-speed digital LSIs such as CPU, graphic processing LSI, and System-on-a-chip, are indispensable for all the today's consumer electrics. However, such today's high performance LSIs require careful debugging for timing related errors and high quality delay fault testing for the dependability. This paper presents time-multiplexed on-chip delay measurement to realize fast and high quality timing...
In modern VLSI and SoC circuits, the minimum power supply voltage is often constrained by data storage elements on the chip. Using an ALU, we show that redistributing the current draw pattern using a delay element within the evaluation period (after known clock skewing techniques have been implemented), can further improve the worst case voltage droop in the power supply by ∼27% at a minimal cost...
This paper presents a construction of dual-edge-triggered flip-flops (DET-FFs) with timing error detection capability. The proposed FF is based on a conventional DET-FF and a conventional timing error detection method. While the conventional timing error detection uses a transition detector with the area of large, the proposed FF uses internal signals in a DET-FF as an alternative of the transition...
With deeply scaled CMOS technology, Bias Temperature Instability (BTI) has become one of the most critical degradation mechanisms impacting the device reliability. In this paper, we present the BTI evaluation of a single inverter gate covering both the PMOS and NMOS degradations in a workload dependent, atomistic trap-based, stochastic BTI model. The gate propagation delay depends on the gate intrinsic...
Post-Silicon Tuning is an emerging technology for improving performance-yield of VLSIs under process variations. This paper focuses especially on the post-silicon timing-skew tuning (PSST) via programmable delay elements (PDEs), and proposes a novel tuning algorithm which utilizes only the result of setup and hold timing tests, not the result of costly delay-time measurements. The basic framework...
A calibrated delay line is a key component in many modern digital systems. Traditionally, these lines are designed as real-time pipelines with static granularity, fine enough to handle a worst-case input rate. However, due to their rigid structure, they have sub-optimal energy for low- and varying-rate input streams. We introduce a complete methodology for designing reconfigurable delay lines which...
We propose a Multi-Vdd Fine-Grained VariablePipeline (MVFG-VP) router in order to reduce power consumptionof Network-on-Chips (NoCs) designed for many-coreprocessors. MVFG-VP router adjusts its pipeline depth (i.e., communication latency) and supply voltage level of each inputand output channel independently. Unlike Dynamic Voltageand Frequency Scaling (DVFS) routers, MVFG-VP routersshare the same...
We consider the model of stochastic timed automata, a model in which both delays and discrete choices are made probabilistically. We are interested in the almost-sure model-checking problem, which asks whether the automaton satisfies a given property with probability 1. While this problem was shown decidable for single-clock automata few years ago, it was also proven that the algorithm for this decidability...
We extend the mean-field (a.k.a. fluid-analysis) approach for massively-parallel continuous-time Markov chains (CTMCs) to models with both Markovian and deterministically-timed transitions. We introduce a new low-level formalism for specifying massively-parallel models with generally-timed transitions, the population generalised semi-Markov process (PGSMP). We then show how systems of coupled delay...
We investigate a number of problems related to infinite runs of weighted timed automata, subject to lower-bound constraints on the accumulated weight. Closing an open problem from an earlier paper, we show that the existence of an infinite lower-bound-constrained run is -- for us somewhat unexpectedly -- undecidable for weighted timed automata with four or more clocks. This undecidability result assumes...
The growing complexity of customizable embedded multi-processor architectures for digital media processing will soon require highly scalable network-on-chip based communication infrastructures. In this paper, we propose xpipes, a scalable and high-performance NoC architecture for multi-processor SoCs, consisting of soft macros that can be turned into instance-specific network components at instantiation...
This paper describes a design and test results of time interval counter (TIC), which provides a high resolution of 10.7 ps within a wide measurement range of 1 ms. To achieve these parameters the counting method with a two-stage interpolation within a single clock period is involved. A sub-gate delay resolution is obtained with the aid of the differential delay line technique. To diminish the nonlinearities...
In this paper, we present an arithmetic Sum-of-Product (SOP) based approach to implement an efficient Discrete Fourier Transform (DFT) as well as an FIR filter circuit. Our SOP based DFT engine uses an improved column compression algorithm, and also handles the sign of the input efficiently. The partial products of the computation are compressed down to 2 operands, which are then added using a single...
This paper investigates the effectiveness of a multi-voltage clock network design that is built using the mesh topology. Unlike a clock tree, a single clock mesh that spans multiple voltage domains is infeasible due to the incompatibility of voltage levels of the clock drivers on the electrically-shorted mesh — each voltage domain requires a separate mesh. These disjoint meshes need to be matched...
This paper presents a methodology to model and analyze the functional behavior of logic circuits under timing variations. In the framework, first a Time Accurate Model (TAM) of the circuit is constructed. The TAM represents the behavior of the circuit in the functional domain under a discrete time model. Afterwards, Variation Logic is inserted to apply the timing variations. Moreover, the circuit...
In this paper, we present an efficient countermeasure against Fault Sensitivity Analysis (FSA) based on a configurable delay blocks (CDBs). FSA is a new type of fault attack which exploits the relationship between fault sensitivity and secret information. Previous studies reported that it could break cryptographic modules equipped with conventional countermeasures against Differential Fault Analysis...
A fast locking 3.0 Gb/s clock data recovery circuit (CDR) based on the digital DLL is proposed for intra-panel clock-embedded display interface. The CDR uses 3-level sub-ranging delay control in digital DLL. Overlapping range selection, successive approximation, and highly-linear timing amplifier are used for most, intermediate, and least significant bits of control, respectively to improve both jitter...
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