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An experimental method was introduced for understanding the exact relationships among polarization, coercive field, and electric field across the ferroelectric layer. They characterized the ferroelectric properties closed inside the metal/ferroelectric/insulator/semiconductor gate stacks. Using the method, we found that N2-dominant-gas annealing process was effective for improving the ferroelectricity...
We propose a 2.1-D SiP that uses an organicinterposer for HBM applications and describe a demonstration of the technology. This SiP structure consists of a newly developed thin photosensitive insulation film multilayer (organic interposer) on a conventional organic package, enabling the package cost to be well controlled. An HBM interconnect was achieved in just two signaling metal layers with an...
This paper describes a systematic approach to design FPGA package for current carrying capability. As we examine silicon, interposer, and package, the profound challenge is found to meet the lifetime of high power device against the greater chance of failures owing to worsen electro-migration in every interconnect level. Our approach consists of practical methodologies to estimate current distribution...
Large 2.5D IC leads the trend for Field Programmable Gate Array (FPGA), graphic, and network application. Chip module (CM) is comprised of top die and Si interposer, and underfill (UF) is fully filled between them. However, coefficient of thermal expansion (CTE) of UF is greater than 20ppm, and CTE mismatch occurs between UF and Si (CTE~3ppm). How to tune chip module warpage is a key for large 2.5D...
Handheld consumer electronics are requiring more complex packaging designs to accommodate higher component densities and reduce form factor. Fan-out wafer-level packaging (FOWLP) has garnered much attention lately as a cost-effective way to achieve high interconnect density and manage larger I/O counts within an affordable package. Two principal approaches to manufacturing FOWLP components have evolved:...
In this paper, finite element method (FEM) simulations are carried out with pillar-concave structure using silicon substrate, silicon substrate with polyimide (PI) and with polybenzoxazole (PBO) for realization of Cu-Cu bonding at low temperature. Parameters of bonding temperature, pillar diameter, concave sidewall angle, and multilayer of concave structure are all considered in simulation. In addition,...
Piezoelectric Zinc oxide (ZnO) have received considerable attention as material for flexible nanogenerator (NG) design due to strong potential for harvesting electrical energy of random body movements at low frequencies (<10 Hz), sonic waves and mechanical vibrations in wide range of frequencies. The vertically integrated NG (VING) structures have been widely investigated as a ZnO-based NG device...
The effect of glass type used as fan-out carrier substrate on the reliability of the electrical devices were investigated. Glasses with thermal expansion coefficient of around 6~8 ppm/K with and without alkali ions involved in the glass were tested. With using non-alkali type glass as the carrier material, it was confirmed that the lifetime of the test vehicles were longer than that heated with conventional...
Aluminum nitride (AlN) is widely used in SAW/FBAR devices, energy harvesting, biosensors, and ultrasonic transducers. The preparation of high-quality AlN film plays the key role on the process integration with CMOS circuits. Here, we report an AlN thin film prepared by RF reactive sputtering at room temperature on substrate with different treatments, which is more suitable and economical for CMOS-compatible...
Fine pitch copper (Cu) pillar bump adoption has been growing in high performance and low-cost flip chip packages. Higher input/output (I/O) density and very fine pitch requirements are driving very small feature sizes such as small bump on a narrow pad or bond-on-lead (BOL) interconnection, while higher performance requirements are driving increased current densities. Assembling such packages using...
The increasing demand for lighter, thinner and flexible electronic devices are resulting in complexity in design. The 2D or planner devices miniaturization is reaching to its limit continuing its complexity in interconnect circuits causing limitation inefficient performance. To overcome the problem of complex interconnection and to introduce the more Compact device, the generation of 3D package rises...
A novel concept for a BCD technology is presented which comprises the processing of the wafer on the thinned backside and which offers — similar to SOI technology — a full dielectric isolation of power devices. Limitations of the breakdown voltage of p-LDMOS encountered in conventional BCD technologies are overcome by replacing the commonly applied deep n well layer by an n+ region formed on the wafer...
A cost effective and reliable technology allowing extreme miniaturization of batteries into silicon, glass chips and electronic packages has been developed, employing a dispense-print process for battery electrodes and liquid electrolyte. Lithium-ion micro batteries (active area 6×8 mm2, 0.2–0.4 mAh) with interdigitated electrodes and glass housing were fabricated, tested and finally compared with...
AlGaN/GaN based high electron mobility transistors (AG-HEMTs) are strong candidates for the future high power and high frequency applications. But the formation of hot-spots and high temperature in these localized regions can limit their applications due to performance degradation and break-down. Understanding the underlying thermal transport processes will be an important step towards solving heat...
The purpose of this work is to study the anti-reflection coating structure with spherical SiO2 micro particles for the single-crystalline silicon solar cell applications. With the single and double SiO2 micro-sphere texturing anti-reflection coating structures, the surface reflectivity of the single-crystalline silicon substrate can be reduced to an average value of 5.8% and 2.85% respectively, in...
We report on micro-machined flow-rate sensors as part of autonomous multi-parameter sensing devices for water network monitoring. Three different versions of the flow-rate sensors have been designed, fabricated and experimentally characterized. Those sensors are made of identical micrometric platinum resistors deposited on two different substrates-glass and silicon with and without insulation layer...
This paper presents the methods of eliminating the plasma-induced Si substrate damage in periphery regions, resulting from high aspect ratio etching process for 3D NAND fabrication. The impact of Si substrate damage is verified by the low and high bias power experiments. The result indicates more Si damage is present with high energy bombardment; therefore, high bias power is recommended to be inhibited...
This paper presents the methods of eliminating the plasma-induced Si substrate damage in periphery regions, resulting from high aspect ratio etching process for 3D NAND fabrication. The impact of Si substrate damage is verified by the low and high bias power experiments. The result indicates more Si damage is present with high energy bombardment; therefore, high bias power is recommended to be inhibited...
In this paper, we have proposed an antireflection coating multi-layers of SiO2/Si3N4 on silicon window, suitable for the infrared range of 8∼12 µm. The 4-layers coating (2-periods of SiO2/Si3N4) with optimized thicknesses was designed using Essential Macleod program developed from Thin Film Center Inc. Based on the proposed long-wavelength infrared silicon-based window by simulation, the samples were...
Due to its independency to the substrate used, Soft mold NanoImprint Lithography (S-NIL) is a technique of great interest in particular for the fabrication of optical devices. We demonstrate a mature pathway for the realization of optical filters from the conception to the optical characterization. Those filters can be realized on large surfaces (up to 6″ diameter wafers) with high conformity on various...
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