The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, silicon/glass/organic interposers for 2.5D/3D interconnects are investigated for signal integrity analysis. As total system bandwidth increases, memory industry has been developed to satisfy its requirements. Therefore, High Bandwidth Memory (HBM) is introduced to the market. HBM enables TeraByte/s bandwidth with extremely fine pitch, short interconnects using Through Silicon Via (TSV)...
Over the last years, singulation of thin semiconductor wafers with (ultra) low-k top layer has become a challenge in the production process of integrated circuits. The traditional blade dicing process is encountering serious yield issues. The seissues can be addressed by applying a laser grooving process prior to the blade dicing, which is the process of reference nowadays. However, as wafers are...
Elastomer stamp micro-transfer-printing is a highly scalable method for the assembly of microscale components onto non-native substrates. One of the key value propositions of micro-transfer-printing is that the transfer stamp can be scaled to wafer-dimensions and can transfer tens to thousands of micro-devices in a single step, equating to multiple millions of units per hour. Here, we report on the...
Silicon interposers are frequently used in memory and network processor systems to closely integrate multiple chips and improve the performance of high-speed systems. The proximity provided by silicon interposer greatly improves bandwidth, power, and latency by simplifying communication and clocking of the links. However, the design of silicon interposer systems poses new challenges in managing the...
Temporary bonding and de-bonding techniques using respectively spin-on glass (SOG) and hydrogenated amorphous-Si (a-Si:H) have been examined for multichip-to-wafer three-dimensional (3D) integration process. In this study, a 280 um-thick known good dies of 5 mm × 5 mm in size were temporarily bonded to a pre-deposited (a-Si:H (100 nm) and SOG (400 nm)) support glass wafer. After completing the die...
We have developed a novel fan-out wafer level packaging (FOWLP) technology for high-performance and scalable flexible and biocompatible substrates that we call FlexTrate (TM). We demonstrate the technology with the assembly of 1-mm-sqaure 625 (25 by 25) Si dielets on a biocompatible Polydimethylsiloxane (PDMS). By using the new FOWLP technology, die-die interconnects with a pitch of 10 mm or less...
Direct metal bonding is a preferred fine-pitch technology for stacking of Si dies in 3D integration. Cu is a metal of choice for direct metal bonding because it is the most common metal for redistribution layer in advanced semiconductor manufacturing, Cu has high conductivity and it is a low cost candidate. However Cu oxidises very fast in air which makes the bonding procedure challenging. In this...
Smaller footprint, thinner packages and simultaneously increased functionality are general requests for all electronic products and as well hold true for MEMS sensors. Current standard packaging technology for MEMS sensors is stacking the ASIC and MEMS silicon dies on a substrate. The sensitive dies are then either protected by over-molding or by attaching some sort of lid. Typical substrate materials...
A technological multi-chip module with a large silicon interposer has been designed, manufactured and characterized for space and airborne applications. It stands for a reconfigurable advanced calculation device, for up to 10 Gbps data rate. The electrical targets are propagation losses less than 2 dB at 5GHz for the signal path across the interposer and its bumps, signal integrity with enough eye...
In this work, the development of engineered silicon substrates for a novel via-middle TSV integration concept is demonstrated. These substrates include 3D buried etch-stop layers which provide both an ideal vertical and lateral etch-stop for TSV trench etching thus enabling the simultaneous realization of different size of TSVs on the same silicon substrate. Beside standard BiCMOS and TSV fabrication...
The interest in wearable electronics has been rapidly increasing due to the high demands for various wearable devices such as smart glasses and smart watches which satisfy the needs of today's customers. Future wearable devices will require fully flexible chip packaging performance and also maintain stable electrical performance under repeatedly bending environment. To meet these requirements, ultra-thin...
This paper presents, for the first time, a novel silicon damascene like via-in-trench (ViT) interconnect for panel-scale package redistribution layer (RDL) configuration. The panel scale damascene RDL in this paper comprises of ultra-fine copper embedded trenches and microvias with diameter equal to the width of trenches using a 5 µm thick dry film photosensitive dielectric. A 140 µm thick glass substrate...
X-Ray Diffraction (XRD) is a very efficient experimental tool for strain/stress analysis at different scales, which makes possible to carry out some mappings in complex 3D flip chip assemblies. First, with single crystal method, both the chip and the substrate have been analyzed at the same positions, considering a 1mm2 step, in order to quantify the level of stress inside. Then Kossel microdiffraction...
Among the technological developments pushed by the adoption of Through Silicon Vias and 3D Stacked IC technologies, wafer thinning on a temporary carrier has become a critical element in device processing over the past years. First generation of adhesive materials enabled the integration of the first devices at the expense of capping the thermal budget. Hence new generation materials are being explored...
In this work we discuss optical coupling technologies for the manufacturing of out-of-plane optics integrated in planar waveguide for interposer-and board-level. Each technology is evaluated on a silicon interposer with optical dielectric through silicon vias (TSV) with SU8 (core) and SiO2 (cladding). First, applying a nanoimprint technology a polymer waveguide has been created with round-shape curvatures...
As power demands for microelectronic devices continue to rise, new techniques for heat dissipation require innovative fabrication solutions such as on-chip cooling methods. The mechanical reliability of these high-powered, high-pressure systems is particularly sensitive to the interfacial strengths within the microelectronic architectures. In research at Georgia Tech, on-chip cooling methodologies...
Plasma Dicing uses Deep Reactive Ion Etch (DRIE), also known as The Bosch Process. This is a well-established "front-end" technology, used in silicon MEMS micromachining and via etching in 3D packaging, which is now finding a new home as a dicing technology in the "back-end" of semiconductor processing. This paper will discuss the key issues and integration challenges. This is...
The Si micro-fluid cooler, combining micro-jet array impingement, micro-channel flow and micro-trench drainage, has been designed and experimentally evaluated. Enhanced jet array impingement has been achieved by eliminating the negative cross-flow effect among adjacent nozzles. Low thermal resistance
High-throughput assembly of miniature wafer-fabricated packages onto panel substrates provides a manufacturing framework for high-performance multi-functional displays and other large-format systems. Control circuits, light emitters, sensors, and other micro-components formed in high-density arrays on wafers use a variety of processes and materials that do not easily translate to large-format panel...
In this paper we present a new approach for building specific packaging that is scalable, versatile and could be potentially cost competitive. Using polymer additive manufacturing, more commonly known as 3D printing, we set out to build customized structures and packages perfectly adapted to component dimensions and specifications. Two different 3D printing technologies, respectively called stereolithography...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.