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Pseudo-lens structures for a fully integrated, stacked open-slot on-chip antenna design for the frequency range around 180 GHz are presented. Due to the use of the silicon substrate as pseudo-lens no reflector or external dielectric lens is required. The antenna is using the multi-layered IHP 130 nm SiGe BiCMOS technology (SG13).
Summary form only given. The complete presentation was not made available for publication as part of the conference proceedings. In this half day tutorial, we present an overview of the JESD204 interface protocol, key performance metrics and challenges in an embedded silicon implementation. We discuss system budgeting of the jitter components in the physical channel and present tradeoffs to meet the...
In wireless multimedia sensor networks (WMSNs), multimedia contents from remote areas are captured by camera sensors (CSs) and sent to data center via cluster heads (CHs) and base stations (BSs) for the purpose of monitoring. The problem in WMSNs is that enabling multimedia streaming, e.g., video streaming, demands high quality and consumes considerable bandwidth and energy resources, meanwhile, the...
Matrix multiplication is one of the most widely used computational kernels in scientific computing and machine learning. Using dedicated circuit for matrix multiplication can reduce the computational time and energy consumption. Traditional matrix multipliers always adopt linear array architecture, which works inefficiently when the size of matrix sub-block is much smaller than the array length. Using...
We propose a digital modulation scheme, based on the generalization of the chirp signal, that allows to improve the performance of Global Navigation Satellite System receivers in scenarios affected by channel additive white Gaussian noise, narrowband interference and multipath. Different signaling schemes, characterized by autocorrelation functions with small secondary peaks, can be obtained by adjusting...
This paper studies the design of standard CMOS two-stage operational amplifiers under power consumption and area constraints. The focus of the work is unity-gain bandwidth optimization, which is achieved by means of a procedure based on numerical analysis that allows determining the optimum sizing of op-amp transistors and the compensation capacitance as well as the best splitting of the allowed bias...
Peer-to-peer (P2P) streaming systems rely on that peers voluntarily share their bandwidth to maintain high performance. Credit-based incentive mechanisms are widely used to encourage peers to share more bandwidth. However, in credit-based mechanisms, how to set a suitable bandwidth price is a critical issue. In this paper, we propose a new dynamic bandwidth pricing mechanism based on Stackelberg game...
Silicon interposer technology enables the integration of multiple silicon dies on it providing fine pitch interconnects for die-to-die communication and Through-Silicon Vias (TSVs) for package/PCB level connections. Therefore, this technology has been identified as a viable solution for logic and memory types of applications where higher bandwidth in required. In the paper, we characterize thick (t=3μm;...
Three-dimensional (3D) integration is considered as a solution to overcome capacity, bandwidth, and performance limitations of memories. However, due to thermal challenges and cost issues, industry embraced 2.5D implementation for integrating die-stacked memories with large-scale designs, which is enabled by silicon interposer technology that integrates processors and multiple modules of 3D-stacked...
As the 3D stacking technology still faces several challenges, the 2.5D stacking technology gains better application prospects nowadays. With the silicon interposer, the 2.5D stacking can improve the bandwidth and capacity of the memory system. To satisfy the communication requirements of the integrated memory system, the free routing resources in the interposer should be explored to implement an additional...
Seamless package-level integration of multiple dies for high-performance computing and networking requires broadband dense die-to-die interconnect. Organic packaging substrates offer lower cost and lower loss interconnect, whereas silicon interposers offer higher density interconnect. In this work, a silicon interposer is fabricated in a relatively inexpensive 0.35 μm CMOS technology as an alternative...
This paper presents a new encoding and corresponding decoding scheme to reduce crosstalk on a high-speed parallel bus. The scheme is based on a modified Fibonacci sequence and is introduced along with potential benefits in some upcoming memory interfaces. The scheme provides appreciable eye opening for interfaces dominated by crosstalk such as existing memory interfaces.
A modeling method to consider simulation switching noise of HBM and its impact on HBM timing is described. This method combines partial element equivalent circuit model for power delivery network and S-parameters based HBM channel model together in HBM studies.
We demonstrate InP-based modified uni-traveling carrier (MUTC) photodiodes (PDs) with top p-contact on silicon-on-insulator (SOI) nano-waveguides. The photodiodes have a low dark current of 10 nA, high internal responsivity of 0.84 A/W and bandwidths up to 35 GHz.
3D interposers are one of just a few ways of making electronic systems faster and more powerful, but their design can be complex. This paper presents a optimization flow to assist the design of silicon interposers with the highest bandwidth density possible. Using the methodology described in this paper, simulations have shown that chip-to-chip links on a silicon interposer can achieve bandwidth densities...
In this paper, we present the performance of the first frequency multiplier using the non-linearity of distributed SIS junctions. The prototype doubler based on distributed SIS junction was for the first time able to pump an SIS mixer. The multiplication efficiency of the distributed SIS junction is 15–30 % for a fractional bandwidth of 10% with excellent spectral line purity. The measured −3 dB line...
In this paper we present 1Gb/s wireless data reception at different sub-THz carrier wave frequencies, using a single quasi-optic Schottky receiver module. The module employs a Log-Spiral broadband antenna patterned on silicon. In this paper we present the performances at carrier wave frequencies ranging from 90 GHz to 330 GHz, demonstrating for the first time the flexibility of the module as versatile...
A 200–225 GHz SiGe combiner Power Amplifier (PA) based on a wideband 4-way power combiner architecture is presented in this paper. The circuit is implemented in a 130 nm SiGe BiCMOS technology with fT/fmax of 250/370 GHz. A parallel power combining architecture based on the low-loss transmission line based zero-degree combiner is used to combine the power from 4 PA cores. At 215 GHz, the Psat is 9...
This paper reports on a measurement which shows for the very first time that uncooled non-quasi static detectors with wide bandwidth integrated in a 32 × 32 pixel focal plane array in standard 65 nm bulk CMOS silicon technology are able to detect non-amplified black-body radiation. With its integrated readout electronics, this “THz camera” shows a noise equivalent temperature difference (NETD) of...
We demonstrated the diaphragm type PZT oscillator performance through simulation experiments. To achieve the desired frequency, firstly, the size of a diaphragm and a thickness of PZT and Si layers are optimized. Then, we select three different PZT/Si models. Finally, we analyze the models transmission efficiency, receiving sensitivity (piezoelectric voltage / electric charge) and frequency bandwidth...
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