The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
An input/output characteristics of the inverter composed of the DNA/Si-MOSFET and the parasitic capacity was studied. The DNA was bridged between the Si electrodes those serve as the source and drain with the 120nm-gap-length. At VDD=0V and VDD=3V, the output characteristic was almost the same. The reason of this phenomenon is that the space charge layer of the DNA/Si-MOSFET changes due to the charge...
I will give an overview of our recent work on the integration of III-V semiconductor nano-structures on silicon (Si) for electronic devices. The template-assisted selective epitaxy (TASE) used to monolithically integrate high crystal quality III-V nanostructures on Si is introduced. The challenges and recent progress of the development of nanoscale III-V MOSFETs and Tunnel FETs is discussed and a...
In this study, we demonstrated an isolated-type flyback converter circuit for high-frequency operations. We estimated the high-frequency characteristics of passive devices in various conditions of a DC-DC converter circuit. We experimentally developed the isolated-type flyback converter circuit and evaluated the frequency response properties. In order to verify the fast-switching operation, the input...
Scaling of silicon MOSFETs has been predicted to go around 10 nm and below. For such a small transistor a gate-all-around nanowire is regarded as an ideal geometry to maintain gate control. On the other hand, such downsizing and excellent gate control has provided opportunities to control individual electrons one by one by placing gates on top of the nanowire to define charge islands and potential...
Utilizing GaN (Gallium Nitride) DC-DC converter for speed control of BLDC (Brushless DC) Motor is investigated in this paper. The proposed system replaces the well-known Si-based switches by GaN FETs which are faster by minimum ten times and much compact that it recedes the size of Switched Mode Power Supply (SMPS) application. The contemplated system uses a GaN-based DC-DC Resonant Converter to drive...
In this paper, we investigated a new device, Hetero-junctionless (H-JL) Double Gate Tunnel Field Effect Transistors (DGTFET) with high-k. III-V semiconductor material (like InAsSi) gives excellent performance when InAs uses at source side, because of low band gap it reduces the potential barrier height of source-channel interface causing maximum carriers are fastly tunneled across the source to drain...
Recently, thermal problem of electronics is becoming more serious, because electronic devices have been downsizing. Especially, since very high electrical field generates in power devices, it is possible that nano-micro scale high temperature hot spots appear in the device. The hot spot temperature has an impact on performance of electronics, and the hot spot has potential of malfunctioning of the...
Thermal models for simulating heating and cooling of PIN diode and FET-based MRI coil blocking circuits are presented. The temperature dependent parameters in the two basic circuit elements as well as the related SPICE-compatible circuit models are discussed. Impedance versus temperature measurements for both PIN diode and MOSFET are presented that confirm the validity of model usage. A MRI coil blocking...
In this paper, I describe the curricular context and some of the distinctive features of the required sophomore/junior-level required course in microelectronic circuits that I have developed and taught at Olin College over the past eleven years. These features include the use of low-cost portable USB instrumentation for the labs, the coverage of CMOS at all levels of inversion right from the start...
One of the major challenge with CMOS circuits with 22nm technology & beyond is to buried the issues of increasing in power dissipation of the circuits due to higher order effects & leakage current. The traditional transistor or MOSFET require significant amount of power so the circuit present on the chip will require a large amount of power due to presence of many transistors in the circuit...
The paper describes, the structural and temperature analysis of 4H-SiC DMOSFET (Double-implanted metal-oxide-semiconductor field-effect-transistor). The SiC based DMOSFETs are most preferred switching devices for high power conversion because of its high carrier mobility and low dopant ionization energy. The current flow is in vertical direction i.e from source in the top to the drain in the bottom,...
In this work, the quadruple active bridge dc-dc converter (QAB) is proposed to be used as a building block to implement the dc-dc stage of a Smart Transformer. Different configuration for this converter are possible and all of them are considered for investigation. Thus, four different architectures of ST, including one based on the Dual Active Bridge (DAB) converter, are presented and compared in...
The purpose of this research effort is to develop a numerical model for a novel tri-material, gate stack engineered double gate MOSFET considering quantum confinement. While developing this model a combination of 2-D Poisson's equation and 1-D Schrodinger equation was used to obtain the potential profile and inversion charge across the complete silicon film. The proposed DG MOSFET structure has been...
Over decades, MOSFET gate length scaling has been the main source of progress in semiconductor electronics. Today, however, the motivation of the industry to continue gate length scaling is declining. On the other hand, researchers still spend considerable efforts on reducing the gate length and on developing ultimately scaled MOSFETs. To this end, both new device architectures and alternative channel...
Gate all around (GAA) nanowire MOSFETs with gate length of 130 nm were fabricated on SOI wafers. The analog performance was analyzed in terms of transconductance, output conductance, voltage gain, Early voltage and transconductance efficiency. The RF characterization showed relatively low cutoff frequency and maximum oscillation frequency. Small-signal parameters are extracted using cold FET method...
We developed a Multi-Subband Ensemble Monte Carlo simulator for non-planar devices, taking into account two-dimensional quantum confinement. It couples self-consistently the solution of the 3D Poisson equation, the 2D Schrödinger equation, and the 1D Boltzmann transport equation with the Ensemble Monte Carlo method. This simulator was employed to study MOS devices based on ultra-scaled Gate-All-Around...
This paper introduces a novel reduced short channel effects in nanoscale SOI MOSFETs by C-shape silicon window inside the channel, source and buried oxide. This work investigates the main characterizations such as maximum lattice temperature, subthreshold swing, DIBL, threshold voltage roll-off which all of them show the superiority of the proposed structure compared to the conventional SOI MOSFET...
Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (<10 nm) and/or very short transistors (L < 50 nm), the kink is totally absent as a consequence of super-coupling...
This paper shows for the first time, the influence of back gate bias (VB) in some analog parameters on pMOS Silicon-On-Insulator (SOI) omega-gate nanowire (ΩG-NW) devices down to 10 nm width (W). An excellent electrostatic control is observed in devices down to 40 nm of channel length. The saturated transconductance slightly increase while the output conductance slightly decrease with VB increment,...
A novel nano MOSFET is reported in this paper to have high electrical performance. In the proposed structure which is named as QSZ-MOSFET, two silicon zones are considered in the channel and buried oxide. The N-silicon zone in the channel region creates a depletion region that increases the current capability. Moreover, the majority of the holes due to the floating body effect could be absorbed in...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.