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Power and Advanced BiCMOS technologies use deep trench architecture to reduce capacitance and leakages that are enhanced by high electric fields and high current applications. In this paper, a power and an advanced BiCMOS technology with deep trench architectures used micro Raman spectroscopy to identify non-uniform stress regions in the circuit. Using this information, architectural changes were...
An automatic, defect-oriented method is proposed for activating latent defects in analog and mixed-signal integrated circuits. Based on the topology modification technique, added stress transistors generate voltage stress that activates these latent defects. This contrasts with burn-in testing which uses increased temperatures as a fault activation mechanism. Moreover, this Design-for-Testability...
A local bending stress is induced by coefficient of thermal expansion (CTE) mismatch between underfill material and metal microbumps in three-dimensional IC (3D IC). A high concentration of filler in underfill is effective to suppress the local bending stress. However, it is difficult to apply high concentration of filler due to fine pitch microbumps. On the other hand, manganese nitride-based compound...
Fine pitch copper (Cu) pillar bump adoption has been growing in high performance and low-cost flip chip packages. Higher input/output (I/O) density and very fine pitch requirements are driving very small feature sizes such as small bump on a narrow pad or bond-on-lead (BOL) interconnection, while higher performance requirements are driving increased current densities. Assembling such packages using...
The increasing demand for lighter, thinner and flexible electronic devices are resulting in complexity in design. The 2D or planner devices miniaturization is reaching to its limit continuing its complexity in interconnect circuits causing limitation inefficient performance. To overcome the problem of complex interconnection and to introduce the more Compact device, the generation of 3D package rises...
The objective of this work is to investigate gate oxide degradation in Lateral Double Diffused metal-oxide semiconductor (LDMOS) devices associated with Polysilicon Buffered Locos (PBL) isolation. It was found that the defects in the silicon at the edge of Polysilicon Buffered Locos resulting in severe degradation of charge-to-breakdown (Qbd) occurring at the edge of the active area silicon have been...
This paper presents a finite element analysis of die attach packaging stress effect on emerging nanomechanical silicon optical filters. The proposed silicon optical filter is composed of Si waveguides and a microring resonator having a few hundred nm in thickness and a few tens of μm in length. Photonic integrated circuit is typically implemented by attaching a new component to a common ceramic interposer...
Two unique gate oxide failure mechanisms are associated with deep trench processes for a 0.18 μm power semiconductor device. One failure mode is a “mini-LOCOS” defect, that is due to inadvertent oxidation of Si in the active area during deep trench oxidation. The other failure mode is due to slip associated with dislocations from the deep trenches. These defects are eliminated by optimizing the SiN...
An innovative TSV approach that removes the historical limitations of Cu and W filled TSVs, making W TSVs once again attractive. Both films have their own advantages and disadvantages. Cu TSVs has two major advantages, one Cu electroplating has the ability to fill high aspect ratio vias enabling a wider via compared to W, and two Cu resistivity is much lower than W enabling a lower resistance via...
Polymer film is general used for stress buffer and dielectric film for Wafer Level Chip Scale Package (WLCSP). Chemical resistance and mechanical resistance of polymer films usually get worse after several processes with chemicals or heat. Weak chemical or mechanical resistance will induce polymer film cracking. Polymer cracking further induces humidity penetration into RDL (Re-distribution Layer)...
Low temperature direct bonding technologies are now widely used for many applications. Mechanisms of some of these technics will be presented. The different way to obtain low temperature direct bonding will then be compared with their respective advantages and drawbacks.
In this study, a low temperature solid state diffusion bonding process with (111) highly oriented nano-twined Cu (nt-Cu) was proposed. A less void bonding interface was observed reveals a good bonding quality for the bonded samples. In addition, a large quasi-single grain was identified in the bondedfilm. Based on these results, it is believed that high strength and durable bonding structure can be...
We have produced a new, automated Maszara testing tool. This tool can be used to measure the bond strength across the entire interface of a bonded wafer pair and produce a bond strength map. The tool can also be used for IR inspection.
In this paper, simulation result of MEMS based micro-hotplate using the finite element method (FEM) has been presented. FEM subdivides a large problem into smaller, simpler parts, called finite elements. The electro-thermo-mechanical behaviors of micro-hotplates have been simulated using INTELLISUITE 8.2.2 software. A composite membrane (SiO2/Si3N4) was used in this case in order to obtain a stress...
As IC technologies continue scaling down, traditional electrostatic discharge (ESD) devices can no longer meet the demands of modern protection, prompting the need for novel device structures. A novel and unique approach to ESD protection using suspended graphene ribbon devices is presented. It has been demonstrated the ribbon's electro-mechanical response to a sudden surge of charge, such as an ESD...
A novel piezoresistive sensitive structure for micromachined high-pressure sensors is proposed. This structure employs several small cavities in a silicon bulk. When high pressure applied on all faces of the bulk, stress emerges between two cavities. The calculation for the variation of the resistance caused by stress in three-dimensional (3D) structure was discussed. According to 3D piezoresistive...
This paper presents a monolithic approach for the integration of silicon nanowires (Si NWs) with microelectromechanical systems (MEMS). The process is demonstrated for the case of co-fabrication of Si NWs with a 10-µm-thick MEMS on the same silicon-on-insulator (SOI) wafer. MEMS is designed in the form of a characterization platform with an electrostatic actuator and a mechanical amplifier spanned...
The ‘BOX creep’ technique consists in introducing stress in a SOI layer by taking advantage of the creep of the buried oxide enabled its low viscosity at high temperature. In this study, we deeply investigate the impact of the structure geometry and parameters on the efficiency of creep through mechanical simulations. We find that a 1.1GPa stress can be achieved for an active length of 400nm. This...
A methodology for the design of canary devices intended for condition monitoring is described in detail for through-silicon vias (TSVs). Two different canaries a geometry change canary and a load-exposure change canary are proposed. To evaluate the proposed canary design qualitatively a comparative finite element study was conducted.
In this paper, a study on electromigration in aluminum bond wires as used in power base station application is presented. Electromigration is shown to occur in three phases and is accompanied by bamboo formation. From accelerated tests, a lifetime model has been determined, based on Black's equation. This enables the prediction of the lifetime of products under high temperature and current conditions.
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