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In this paper we study the circuit design implications of Ge vs. Si PMOS FinFETs at the 10 and 7nm nodes, using TCAD calibrated statistical compact models and the ARM predictive benchmarking flow. The ARM predictive flow incorporates advanced-node-relevant layouts, design rules, parasitic RC extraction and wire-loading. We present the first comprehensive simulation study evaluating Ge pFinFETs in...
Post-silicon validation is an important step in the chip design life cycle. This involves observing the signal elements of the chip to check if the signals have the expected values. The process essentially requires observing the circuit behaviour (i.e. the signal values) on giving known inputs, and checking for correctness and conformance. The size of the trace buffer which stores the values of the...
2.5D integration based on interposer technologies provides high density integration and high system bandwidth. Among many materials for the interposer substrate, glass could be a promising material since it provides low signal loss and its ultra-thin thickness. When chips are stacked on the glass interposer, power distribution network impedance of 2.5D IC must be estimated, analyzed and optimized...
This paper proposes closed-form expressions of parasitic parameters in a silicon substrate that consider substrate contacts. In general bulk CMOS technologies, the standard cells with bulk (substrate and well) contacts or tap cells for bulk contacts are used in physical layout designs. As tap cell placement methods, there are dense random placements and sparse regular placements in cell rows vertically...
In this paper, we introduce a fast and accurate 3D thermal analysis methodology for sequential face-to-back (F2B) and parallel face-to-face (F2F) 3D integration technologies. Our proposed models take design floorplan and the corresponding power map with temperature-dependent leakage power component and accurately estimate the temperature of any given location in the design. We show that our models...
Surface-Evolver is an interactive program used to study surface profiles that are influenced by surface tension. The tool is an open source software, developed by Professor Kenneth Brakke in Susquehanna University, USA. Solder based self assembled (SBSA) 3D structure was studied previously via experiments using lithography, deposition, wet etching, and dip soldering methods. SBSA 3D structure has...
Through silicon via (TSV) based 3D-IC is the key technology to satisfy the continuously growing demand on lower power consumption, higher system bandwidth and smaller form factor of electronic devices. As the I/O count increases up to the order of tens of thousands for high speed data transmission, TSV diameter and interconnection pitch are reduced, which may cause various defects throughout the channel...
Diffusion through graphs can be used to model many real-world process, such as the spread of diseases, social network memes, computer viruses, or water contaminants. Often, a real-world diffusion cannot be directly observed while it is occurring -- perhaps it is not noticed until some time has passed, continuous monitoring is too costly, or privacy concerns limit data access. This leads to the need...
Recently, significant work has been carried out to develop a technology based on 4H-SiC semiconductors aimed to utilize the unique physical and electrical properties of this material to achieve improved performance in high-power and high-temperature electronic circuits. This work is an effort to develop an analytical model for the 4H-SiC based n-channel enhancement mode MOSFET (NMOS). Here, a simple...
Silicon fault diagnosis, the process of locating faults in a chip prototype, becomes more challenging and time-consuming with increasing design complexity. Consistency-based fault diagnosis aims at identifying fault candidates for an erroneous execution trace by symbolically checking the consistency between the golden gate-level model and the faulty behavior of the prototype chip. The scalability...
Lumped analytical electrical models for partially cracked and void hole defected TSVs are proposed in this paper. Accurately modeling defects may enhance the test methodology and could be vital to improve the quality of TSV-based 3D-ICs. These models were verified by simulations using a commercial 3D resistance, capacitance and inductance extraction tool. The presented simulation results are in close...
Three-dimensional integrated circuits (3D ICs) provide a promising solution for overcoming delay/power problems of 2D ICs by stacking chips vertically. Signal propagation speed among the stacked chips is very important for 3D IC systems. We propose a simple model for analyzing the vertical signal propagation in through-silicon-via-based 3D ICs and discuss the impact of physical parameter variations...
3D integration technology has the potential to enhance IC performance, improve functionality and lessen wiring of ICs. However, it poses several challenges, where the key challenge is heat generation from internal active layers due to power dissipation. To mitigate this challenge, thermal aware design has become a necessity. Towards thermal aware design, this paper proposes a two stage design technique...
An integrated passive power combiner is discussed and characterized based on test structure fabricated in a 150 nm LFoundry CMOS process. The power combiner uses differentially driven coupled transformers as a basic building block. We discuss first the constraint driven sythesis of the transformer itself and the device modeling with a rapid RLCk model extractor. Helic's electronic design automation...
In this paper, we propose a method to analyze the scattering parameters for coupled microstrip lines with bend discontinuities. The key idea of the proposed method is to analyze the coupled bends and parallel coupled lines individually. Specifically, the equivalent π circuit model is built to approximate coupled bends and the corresponding scattering matrix is obtained by converting Z-matrix; the...
Piezoelectric microelectromechanical systems (MEMS) resonators on Si can be a potential candidate to replace discrete L-C components in series resonant converters. In this paper, ring shaped piezoelectric (AlN) micro-resonators on Si are reported. Having vibration in contour mode, these resonators can achieve resonant frequency as low as 87.28 MHz. Recently, we have fabricated high Q (>1000) piezoelectric...
This paper presents an ideal lumped-element equivalent circuit model for on-chip monolithic transformers on silicon substrates. R, L Foster networks in a T-topology are used to capture the frequency-dependent proximity and skin effects in the transformer windings as well as substrate eddy-current effects and, hence, the complete frequency-dependent self and mutual impedances of the transformer. The...
Models for cache yield and coverage for radiation-induced soft errors quantify the trade-off between the minimum supply voltage (VMIN) and the soft-error protection when applying error-correcting codes (ECC) to a cache. Model predictions of the VMIN benefit and soft-error coverage agree closely with silicon measurements from a 7Mb data cache in a 20nm test chip when considering either single-error...
Two-dimensional finite difference time domain (2D-FDTD) method is a very powerful electromagnetic numerical method for simulating electromagnetic(EM) problems of a complicated printed circuit board (PCB). However, due to the lack of transversal components of electric field intensities, it is hard to contain the coupling effect among isolated power/ground islands. In order to simulated the EM performance...
Through mechanical coupling, thermal effects can lead to drift in circuits' electrical performances, as well as integrated circuits reliability issues. It is thus necessary to consider thermal, mechanical and electrical effects all together in a self-consistent manner, This work focuses on the electro-thermo-mechanical simulation of integrated circuits in the target of ICs reliability monitoring from...
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