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In the context of the dataflow process network mapping problem, we propose a parallel solutionmethod based on a semi-greedy heuristic to improve the solution quality of a greedy regret-based mapping algorithm (RBA). In this method, several executions of a randomized version of RBA are performed in parallel togenerate different solutions. We exploit a correlation between solution quality and execution...
As multiprocessor systems are continuing to be adopted in academic laboratories and industry, researchers and application developers are routinely designing multiprocessor systems from the low level. Before they can validate their ideas, most of their time is spent on handling massive engineering details. It includes building a multiprocessor system from scratch by handling details of IP components...
Modern technologies of integrated circuits allow billions of transistors arranged into a single chip, enabling to implement complex systems, which need a scalable and parallel communication architecture. Network-on-Chip (NoC) is a natural candidate to fulfill such communication requirements, providing high performance when the communication demands are balanced. This work proposes a new static balancing...
A well-known technique for enhancing the performance and stability of content distribution is the use of multiple dissemination flows. Multipath TCP (MPTCP), the most popular multiflow protocol on the Internet, allows receivers to exploit multiple paths towards a single sender. Nevertheless, MPTCP cannot fully exploit the potential gains of multipath connectivity, as it must fairly share resources...
The so-called 5G networks promise to be the foundations for the deployment of advanced services, conceived around the joint allocation and use of heterogeneous resources, including network, computing and storage. Resources are placed on remote locations constrained by the different service requirements, resulting in cloud infrastructures (as pool of resources) that need to be interconnected. The automation...
The Network-on-Chip (NoC) architecture has been seen as an interconnect solution for complex systems. However, performance and energy issues still represent limiting factors for Multi-Processors Systems-on-Chip (MPSoC). In order to match low power and high performance, hierarchical NoCs have been proposed, with interconnecting clusters of IPs tailored to application specific domains. In the near future...
Newest technologies of integrated circuits fabrication allow billions of transistors arranged in a single chip enabling to implement a complex parallel system, which requires a high scalable and parallel communication architecture, such as a Network-on-Chip (NoC). These technologies are very close to physical limitations increasing faults in manufacture and at runtime. Thus, it is essential to provide...
This paper presents PTNet, a new data center topology that is specifically designed to offer a high and parameterized scalability with just one layer architecture. Furthermore, despite its high scalability, PTNet grants a reduced latency and a high performance in terms of capacity and fault tolerance. Consequently, compared to widely known data center networks, our new topology shows better capacity,...
Todays data centers may contain tens of thousands of computers with progressively more specialized and expensive equipments. Thus, the research community has proposed various interconnect topologies e.g FatTree, Dcell and Bcube. However, these architectures are too complex and very expensive to construct and they suffer from high average path length (APL) and latency. Motivated by these challenges,...
Industrial control systems (ICS) are defined with hardware and software components dedicated to control and monitoring tasks for factory process. Proper functioning of ICS architectures is mainly linked to the performance they offer. System integrators (SI) must know performance of the architecture they propose to the customers by assessing them. Many methodologies have already proven their capabilities...
A routing algorithm plays a critical role in the performance of a Network — on — Chip architecture. An apt routing strategy should cater the performance demands expected from the network, and also the algorithm should be able to scale up seamlessly as the network grows in size. Keeping this in back drop, an attempt is made in this paper to develop a fully grouped routing for Homogeneous Fat Tree Network...
Network management is one of the biggest challenges in operating the Internet network today. This is mainly due to its complexity and inflexibility, which result from the tight coupling of the control plane and data plane. Efforts to address this challenge have led to the introduction of Software Defined-Networking (SDN), an emerging architecture in which a logical single controller controls the behaviour...
Software Fault Tolerance is an ability of computer software to continue its normal operation despite the presence of system or hardware faults. Most companies are moving towards a microservices-based architecture where complex applications are developed with a suite of small services, each of which communicates using some common protocols like Hypertext Transfer Protocol (HTTP). While this architecture...
Vehicular adhoc networks come out to be a promising solution for ensuring traffic and road safety on highways. However this area induces communication challenges such as topology dynamics, and connectivity losses. Today's Vanet demand a sound planning to make architectural level decisions. Integrating Vanet with emerging Software defined Networking brings ground-breaking networking innovation. Recent...
Addressing, routing, and forwarding in the Internet must form a coherent architecture that satisfies user and technical requirements, such as performance, robustness, and efficiency. This paper presents the Core-Rooted Path Addressing (CRPA) architecture, which is a novel combination of mostly known architectural components. CRPA is designed as a network layer for physical topologies and combines...
In complex biological systems, the hypothesis that bio-diversity contributes to stability or robustness is an active debate. The FP7 DIVERSIFY project tests whether this hypothesis holds for software systems, and explores the use of diversity as a heuristic to increase robustness in self-adaptive architectures. Inspired by Ecology, we present here a technique to evaluate diversity of software architectures...
On-chip communication architectures play an important role in determining the overall performance of System-on- Chip (SoC) designs. Communication architectures should be flexible so as to offer high performance over a wide range of traffic characteristics. In state-of-the-art multi-processor systems-on-chip (MPSoC), interconnect of processing elements has a major impact on the system's overall average...
This paper proposes a hierarchical battery balancing architecture for the series connected lithium-ion batteries. The battery cells are grouped into different packs and the bottom layer is the Adjacent Cell-to-Cell structure consisting of the packs. The top layer is connected to different packs and can deliver the energy from one pack to any other pack bi-directionally, leading to high flexibility...
Today's multimedia, wireless applications increasing complexity which is motivation for the system designers to innovate continuously. The strongly emerging class Coarse-Grained Re-configurable Architecture (CGRA), is currently receiving high attention. CGRA has excellent performance with flexibility in fabrication techniques. Reconfigurable fabric (RF) is main part of CGRA processor. This paper gives...
The scaling of semiconductor technologies is leading to processors with increasing numbers of cores. A key enabler in manycore systems is the use of Networks-on-Chip (NoC) as a global communication mechanism. The adoption of NoCs in manycore systems requires a shift in focus from computation to communication, as communication is fast becoming the dominant factor in processor performance. Many researchers...
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