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Analog circuits automatic evolutionary design is a method of designing analog circuits automatically, how to code the circuit is the primary problem in the analog circuits evolutionary design. In this paper, a new analog circuits coding method is proposed, it is designed by imitating the generation process of the special connected and closed weighted undirected graph, we name it generating coding...
A fully integrated and packaged Power Amplifier (PA) has been realized in 130nm STMicroelectronics H9SOIFEM. The PA is based on a new dedicated power cell delivering very good RF performances. At 28dBm output power, ACPR is −40dBc and PAE is 40%, reaching a FOM (ACPR+PAE) of 80 at 1.95GHz 3G standard, under 3.4V. Neither linearization nor efficiency enhancement technics have been used. The core power...
A full range current sensor based on self-bias structure for buck regulator is presented in this paper. The proposed full range current sensor can sense current from both the high side and low side switches of the power regulator within the same switching cycle with input current varying from 50 mA to 500 mA. It has higher than 95% sensing accuracy while consuming less than 1% of the total input power...
This paper presents a DC-RF power inverter that efficiently synthesizes high-voltage RF waveforms directly from a battery voltage using thin-oxide CMOS switches. Instead of stacking transistors or employing large inductive transformation ratios, high output power is generated by switching individual class-D power amplifier (PA) cells in a 2-phase house-of-cards (HoC) topology to provide voltage addition...
This paper presents an analytical investigation of the three-phase single active bridge DC-DC converter. First, multiple operation modes have been identified, that can be distinguished by the shape of the phase currents. For every single operating mode, analytical equations have been derived in order to describe the currents of both input and output bridge. In this paper, two operating modes are selected...
By combining a switched-capacitor cell with a switched-inductor cell, a new passive switching cell is defined. It is inserted in basic converters to get step-up regulators providing a large dc gain as required in applications powered by environmental-friendly sources of energy. Simulation and experiments show the superiority of the proposed converter compared with available solutions with the same...
A continuous-time ΔΣ ADC with a new high-linearity Gm-cell is presented. A loop filter employing a Gm-C filter is preferable to an active-RC filter with op-amps for low power consumption and a large phase margin. However, distortion caused by the Gm-cell degrades the ADC performance. A cascoded flipped voltage follower Gm-cell is proposed in order to address this problem. Simulation results reveal...
A wideband 2–3 GHz three-stage low noise amplifier (LNA) featuring current reuse, cascaded L-match input network, and multiple gated transistors method (MGTR) is designed in 0.18-μm CMOS technology. The current-reused topology is adopted to fulfill low power consumption, meanwhile, high gain and low noise are obtained. The cascaded L-match input network is used to enhance the input matching bandwidth...
The paper presents fault tolerant control algorithms of modified space vector pulse width modulation (SVPWM) for three-phase inverter supplies a PMSM in case of failure of one transistor leg. Fault tolerant inverter structure with four-switch is analyzed with taking into account the non-ideal DC link. Calculations of the desired voltage vector in the PMSM drive are presented. An optimal voltage vector...
Advancement in wireless and microsystems technology have ushered in new devices that can directly interface with the central nervous system for stimulating and/or monitoring neural circuitry. In this paper, we present an ultra low-power sigma-delta analog-to-digital converter (ADC) intended for utilization into large-scale multi-channel neural recording implants. This proposed design, which provides...
This paper presents a single-pole single-throw (SPST) switch operating over the entire WR-3 band. The SPST switch is composed of two shunt transistors and transmission lines in between to resonate the off capacitance of the transistors. The switch is implemented using a 250-nm InP DHBT technology. The measured insertion loss and isolation are no more than 2.9 dB and 13.1 dB, respectively, from 220...
A 290-GHz heterodyne integrated imager has been developed in a 65-nm CMOS technology. The imager consists of a mixer, an LO (local oscillator), an IF amplifier, and an IF detector. A responsivity of 20 kV/W and a noise equivalent power (NEP) of 29 pW/Hz1/2 were measured. Images were successfully acquired with an image acquisition setup that employs the fabricated imager circuit.
In this paper, a new topology for a third order quadrature oscillator (QO) using a new active element, voltage differencing buffered amplifier (VDBA) is proposed. The proposed QO topology is implemented using a meld of lossless and lossy integrators that produce sinusoidal oscillations equally spaced in time with phase shift of 90 degrees. The functionality of the proposed QO is verified with the...
This paper presents the implementation of a compact R-2R Digital-to-Analog Converter (DAC) for BIST applications of analog and mixed-signal circuits. It focuses on evaluating the DAC design requirements and its possibilities in structural and alternate test methodologies. More concretely, the aim of the paper is the low-cost generation of digitally programmable DC voltages for parametric deviation...
In the present paper, an operational amplifier (Op-Amp) topology that achieves high-gain and low-power dissipation is designed and analyzed. The design uses a current mirror with a class-A output stage having capacitive Miller compensation. The low power operational amplifier is the main active power consuming block. The proposed Op-Amp operates at ±0.75V supply voltage and consumes a total...
This paper presents a new circuit realization capable of simultaneously realizing all three current-mode first-order filtering functions, namely the low-pass (LP), high-pass (HP), and all-pass (AP). The proposed circuit is created using three programmable current amplifiers (PCAs) and only two passive components, which includes one resistor and one capacitor. LP and HP filters have independently tuneable...
Last few decades have shown that the low-voltage (LV) low-power (LP) IC designs have been given a great attention as power consumption has become a great challenge. This paper demonstrates implementation of OTA and its application in low pass filter design using bulk-driven MOS transistors (MOST), bulk-driven dynamic threshold MOST, bulk-driven floating-gate MOST and bulk-driven quasi-floating-gate...
A circuit analysis of the Low Noise Amplifier (LNA) topology with transformer-based input integrated matching is carried out. The analytical expressions for input impedance, transconductance gain and noise figure have been derived and compared with those of the most widespread LNA topology, i.e. the cascode LNA with inductive degeneration. Finally, two LNAs operating at 24 GHz have been designed in...
A novel class-AB Flipped Voltage Follower is proposed, suitable for low-voltage low-power CMOS implementation in advanced technology nodes. Simulations have been performed using STMicroelectronics models for the 45nm technology. The Flipped Voltage Follower allows low output impedance and high linearity by means of a feedback loop. However, like the conventional common-drain voltage follower, it has...
This paper presents a comparative analysis of the energy characteristics of two topologies multilevel semiconductor converters: a three-level voltage source inverter and two-zone current source inverter. Computer simulation was used to obtain energy and control characteristics of studied converters. Harmonic distortion was used as the primary evaluation criteria to compare the quality of output voltage,...
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