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Design space exploration is crucial to an optimal application mapping in Network-on-Chip. However, the optimality evaluation of the explored solution has been neglected in previous studies. In this paper, we propose an efficient and credible statistical estimation approach to evaluate the optimality of explored solutions with respect to the mapped communication, which is directly related to power...
Network-on-Chip (NoC) is considered to be a promising approach to implement many-core systems and a large number of on-chip router optimization studies have been proposed. In this paper, we propose to dynamically adjust link-width of each port on a router optimized to spatially biased traffic. Different from the previous No Coptimization approaches, in which the optimization is almost performed in...
This paper aims to present a development environment that enables the automatic code generation amenable for the interconnection of components obtained as a result of the partition of a Petri net model addressing its distributed execution using networked controllers (including microcontrollers and FPGAs devices, as well as specific controllers based on PLCs and general purpose PCs). The proposed interconnection...
This article presents the design of RecoNoC: a compact, highly flexible FPGA-based network-on-chip (NoC), that can be easily adapted for various experiments. In this work, we enhanced this NoC with dynamically reconfigurable shortcuts. These can be used to alter the NoC's topology to adapt to the system's communication needs. The design has been implemented and tested on a Xilinx Virtex-2 Pro FPGA,...
Despite its significance to embedded systems industry and research communities, little research has been done on providing guarantees for hard real-time applications running over multicore processors based on wormhole Networks-on-Chip (NoCs). This work takes advantage of recent work on schedulability analysis that is tailored to such platforms, and uses it as a ranking function in a genetic algorithm...
In order to eliminate the inefficiency of the conventional bus based architecture, network-on-chip (NoC) has been suggested as a novel approach for several years. Considering the trend that hundreds or even thousands of IP blocks will be integrated on a chip, the concept of multi-cluster NoC is proposed. It usually adopts the hybrid architecture mixed with bus based local system and mesh based global...
This paper proposes a fast full-chip synthesis methodology which can be built a custom Network-on-Chip (NoC) topology for NoC-based systems. The processors and their communications are synthesized simultaneously in the system-level floorplanning process. The proposed method leads to accurate area estimation, which makes an algorithm much more efficient than previous approaches. Moreover, the wirelength-aware...
Large and complex system-on-chip devices consisting of many processor cores, accelerators, DSP functions and many other processing and memory elements are becoming common in the semiconductor industry nowadays. To communicate, these processing and memory elements need to have a network-on-chip (NoC) that is scalable enough to support large number of elements and large bandwidth among other requirements...
Asynchronous switching is proposed to achieve low power Network on Chip. Asynchronous switching reduces the power dissipation of the network if the activity factor of the data transfer between two ports αd is less than A αc + B αclk. Closed form expressions for power dissipation of CLICHE topology are provided for both synchronous and asynchronous switching. The area of the asynchronous switch is...
The emergence of the third dimension in Network-on-Chip (NoC) design as a quest to improve the quality of service (QoS) of on-chip communication has evolved with enormous interest. However the underlying router architecture of 3D NoCs have more area footprint than 2D routers. In this paper, we investigate heterogeneous 3D NoC topologies with the focus on finding a balance between the manufacturing...
This paper describes a high performance neural processor by using a Network on Chip (NoC) architecture to solve the interconnection and performance problems in hardware neural networks. The proposed NoC-based neural processor is composed of 20 tiles in 4×5 2-D array, and each tile includes a Process Element (PE) and a packet switched router. In each PE, four neurons are implemented to achieve low...
Due to the advancement of VLSI (Very Large Scale Integrated Circuits) technologies, we can put more cores on a chip, resulting in the emergence of a multicore embedded system. This also brings great challenges to the traditional parallel processing as to how we can improve the performance of the system with increased number of cores. In this paper, we meet the new challenges using a novel approach...
This paper addresses the problem of application mapping for Mesh-of-Tree (MoT) based Network-on-Chip. It proposes a new algorithm based on Kernighan-Lin partitioning to identify closely related cores of the application. The nodes are then mapped to the topology using another heuristic algorithm. The MoT mapping results have been compared with the mesh-mapping results reported in the literature for...
In recent years, the rise in the number of cores being integrated on a single chip has led to a greater emphasis on scalable communication fabrics that can overcome data transfer bottlenecks. Network-on-Chip (NoC) architectures have been gaining widespread acceptance as communication backbones for multi-core systems, due to their high scalability, predictability, and performance. However, NoCs are...
Network on Chip is an efficient on-chip communication architecture for SoC architectures. It enables the integration of a large number of computational and storage blocks on a single chip. The router is the basic element of NoC with multiple, connecting to other router and to a local IP core. This router architecture can be used later for building a NoC with standard or arbitrary topology with low...
This paper presents a method to extract global order of transactions from local partial orders in NoC tiles. The ordering method is based on our set of “happened-before” rules, assuming transactions do not have a timestamp. The assumption is based on the fact that implementation and usage of a global time as timestamp in such systems may not be practical or efficient. We have improved the extracted...
Network-on-Chips (NoCs) have emerged as a paradigm for designing scalable communication architecture for System-on-Chips (SoCs). In NoC, one of the key challenges is to design the most power-performance efficient NoC topology that satisfies the application characteristics. In this paper, we present a three-stage synthesis approach to solve this problem. First, we propose an algorithm [floor-planning...
This paper presents a novel application mapping strategy onto the Butterfly Fat Tree (BFT) topology for Network-on-Chip (NoC) design. It proposes a Kernighan-Lin bi-partitioning strategy to identify the closeness of cores by analyzing their bandwidth requirements. The nodes are then mapped to the BFT topology. The BFT mapping results have been compared with mesh-mapping results reported in the literature...
A Network-on-Chip (NoC) is a new paradigm in complex System-on-Chip (SoC) designs that provides efficient on-chip communication architecture. It offers scalable communication to SoC and allows decoupling of communication and computation. In NoC, design space exploration is critical due to trade-offs among latency, area, and power consumption. Hence, analytical modeling is an important step for early...
This paper addresses the CAD subsystem providing System Design of Irregular network-on-chip. The optimization objectives include System on chip those addressed to Network of chip (NoC).
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