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This paper presents an improved ISI shaping technique for multi-bit ΔΣ DACs. Compared to the prior ISI shaping method (Lars Risbo et al, JSSC, 2011) that monitors only the up (0 → 1) transitions, the proposed technique makes use of both the up and down (1 → 0) transitions with negligible hardware cost. It provides a finer control of the transition activity, thereby improving the ISI shaping effect...
We present a fully-digital digital-to-analog converter (FD DAC) architecture design for high-speed communication systems. The FD DAC design is based on the ΔΣ modulation. The specifications for the DAC includes a low 1.2 V supply voltage, a high 5 GS/s input sampling rate, and a wide 2.5 GHz bandwidth. We employ a combination of the time-interleaving, parallel, and pipelining techniques to reduce...
This paper presents a variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers. The proposed design generates the 3-level signal without a ½VDD driver, thus removing all the overhead and hassle of an additional supply. Moreover, the proposed all-digital scheme uses half the clock frequency while maintaining the same data rate of the conventional...
Prototyping distributed embedded system can be seen as a collection of many requirements covering many domains. System designers and developers need to describe both functional and non-functional requirements. Building distributed systems is a very tedious task since the application has to be verifiable and analyzable. Architecture Analysis and Design Language (AADL) provides adequate syntax and semantics...
The paging mechanism is widely used in most modern systems to handle the virtual memory. Many page replacement algorithms have been proposed. Therefore, the cor-rectness and reliability of virtual memory management systems become very important. It is essential to formalize and verify the system in a formal way. In this paper, we model the virtual memory management system with MSVL, which is a parallel...
Techniques using modification of power supplies to attack circuits do not require strong expertise or expensive equipment. Supply voltage glitches are then a serious threat to the security of electronic devices. In this paper, mechanisms involved during such attacks are analyzed and described. It is shown that timing properties of logic gates are very sensitive to power glitches and can be used to...
In this paper, a counter based all digital frequency divider is presented. The architecture is based on a counter and a control logic which controls the division ratio. Depending on the control logic circuitry, phase shifting of divided clock signal is also possible. By utilizing both divided signal and shifted signal, fractional ratios are implemented. Phase shifting relies on division factor. Key...
This paper proposes HSTL based energy efficient design of frame buffer for a digital image processor. Our aim is to make energy efficient frame buffer design and for that reason we are using different types of HSTL IO standards. This design is implemented on both Virtex-6 FPGA and Airtex-7 FPGA and compared the power dissipation. It is observed that at 1GHz operating frequency, there is maximum IO...
In this paper, we are implementing green Integrator. Digital integrator is an analog to digital converter. Which is designed in Xilinx ISE14.6 using various IO standard of SSTL in 28nm Kintex-7 FPGA. We are comparing different IO standard of SSTL to get minimum IO power. Via SSTL technology, we achieve green computing with respect to low voltage impedance. We are using different classes of SSTL in...
Phase-Locked Loops (PLLs) are widely used as frequency synthesizers for clock signal generation. In aerospace environment, however, the performance of the PLL can be degraded due to the radiation exposure, which causes degradation of the parameters of its components. Thereby, this article presents a performance analysis of a clock generator PLL under TID effects. Output frequency, power consumption...
In this paper we are presenting result of simulation based energy efficient bi-directional visitor counting machine (VCM) on FPGA (Field Programmable Gate Array). In this work, we have used Xilinx software. We have used different IOs standards that include HSTL_I, HSTL_II, HSTL_I_18, HSTL_II_18, LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25, and LVCMOS33. For these IOs standard we have collected the total...
In this paper, a throughput-driven design technique is proposed, in which a suspicious timing error prediction circuit is inserted to monitor the signal transitions at some selected check points. Unlike previous works where timing errors are detected after their occurrence, the proposed method tries to use the real intermediate signal transitions for timing error prediction. The check point selection...
The current work proposes a low emission frequency shift keying (FSK) non-PLL based modulator for transmitting neural signals. FSK has been shown to be viable alternative to widely used ASK (Amplitude Shift Keying). Designers need to start developing low Electromagnetic Interference (EMI) algorithms for implanted devices so as to minimize interference. The proposed algorithm utilizes a ramp to modulate...
Testing of VLSI chips are becoming very much complex day by day due to increasing exponential advancement of nano technology. So both front-end and back-end engineers are trying to evolve a system with full testability keeping in mind the possibility of reduced product failures and missed market opportunities. BIST is a design technique that allows a system to test automatically itself with slightly...
Distributed systems can be characterized by processes that communicate with each other by message passing, through communication channels, and may be located at several computers spread over a communication network. These processes and communication channels are usually characterized by synchronous or asynchronous timeliness behavior, according to the characteristics of underlying system (operating...
This paper presents a clock generator featuring a feedback temperature and voltage compensation circuit and low dropout regulator circuit on-chip capable of constraining frequency variation to 3.49 %. The inclusion of an OPA, MOS transistors and resistors eliminates the need of large BJT devices to reduce the area penalty and achieve low power consumption. Particularly, a negative feedback temperature...
The satellite clock offset is crucial for simulation of Global Navigation Satellite System (GNSS). The accurate and efficient models are required to generate the satellite clock offset in real time. This paper proposed a scheme that generates satellite clock offset with white noise as input. Furthermore, the computation of model parameters is presented with the original satellite clock data. The simulation...
A method of serial links output data and clock signals setup and hold times correction presented in this paper. The proposed architecture produces corrected clock which have enough setup/hold time margins respect data signal over PVT, which is needed to avoid data errors and setup/hold violations during further operation with data. The presented correction mechanism can be used in the special input/output...
The development environments for Hardware Description Languages (HDLs) are essentially meant and designed for highly trained professionals/ engineers and as such are not suitable for use as an introductory tool for students learning HDLs. With students adopting a variety of operating systems, there is a need for a light-weight and cross-platform environment. Further, such a development environment...
To achieve ultra-high-speed image sensing faster than 1-giga frames per second, a multi-aperture high-speed imager is proposed. In this paper, the architecture of the imager and a design of digital circuits are presented. Basic operations of the digital circuits are verified by a fast SPICE simulator, NanoSim by Synopsys. Arbitrary shutter pattern of 128 bits and the number of repetition can be reprogrammed...
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