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As semiconductor feature sizes continue to shrink and outstrip lithography advances, the nature of manufacturing defects has evolved from hard faults to a more subtle lithography-driven form where its impact results in marginal circuit behavior, giving rise to so-called marginal defects. Due to the increasing divergence between test and system modes of operation in complex system-on-chip (SoC) devices,...
Recently paper-based microfluidic chips have been proposed to achieve microfluidic analysis for many applications. Such chips achieve "lab-on-paper" instead of traditional "lab-on-chips". The paper substrate is attractive because it is cost-effective, easy to use and disposable, fully compatible with most medical/biochemical applications, and offering liquid flow by capillary without...
Built-in self-repair (BISR) concept is widely utilized and proven by industry to increase the reliability of regular structures such as memory cores. The idea of using this concept in mostly irregular structures such as logic cores is quite new and represents a challenging task with many problems involved; e.g. the identification of regular parts in a logic core suitable for reconfiguration, excessive...
The major causes of board manufacturing defects are: missing components, wrong components, mis-oriented components, broken track (opens), shorted tracks (track-to-track shorts), pin-to-pin solder opens, pin-to-pin solder shorts. To consider the shorts, we assume that the behavior of any short is logical i.e. the short behaves as if it were an unwanted wired-AND gate (strong 0, weak 1) or wired-OR...
This paper presents DrSEUs (Dynamic robust Single-Event Upset simulator), a novel fault injector that uses the Simics full-system simulator. Fault-injection testing enables the use of commercial off-the-shelf (COTS) processors in space, which are susceptible to radiation-induced faults but are desirable due to the lower cost and higher performance of COTS devices. The de facto standard for fault injection...
In this paper we proposed a new approach for detection of faults in linear analog VLSI circuits. Our approach is very simple and efficient which is based on Signal Flow Graph. This approach is also used to calculate the tolerance of the component which is very important parameter of any VLSI circuit. In this paper we describe the whole method for testing of linear analog VLSI circuits and this approach...
In this paper we proposed a new approach for detection of faults in linear analog VLSI circuits. Our approach is very simple and efficient which is based on Signal Flow Graph. This approach is also used to calculate the tolerance of the component which is very important parameter of any VLSI circuit. In this paper we describe the whole method for testing of linear analog VLSI circuits and this approach...
With the increasing demand of super high scale of integration and small form factor in advanced semiconductor products, especially those that integrate DRAM and logic dies, 3D IC and Wafer-Level Chip-Scale Packaging (WLCSP) are considered promising approaches. In Integrated Fan-Out (InFO) WLCSP, a large number of fine-pitch pads, where neighboring pads cannot be probed simultaneously due to insufficient...
In today's fast growing and increasing complex world of VLSI circuits, test quality has significant effect on the quality of the product. A malfunctioning circuit is a result of design flaw, manufacturing defects or both. Testing is used as a measure to estimate the quality of design. High quality testing minimizes defect-per-million (DPM) and thus can significantly reduce manufacturing costs and...
In this paper, we have presented an online testable full adder and an online testable n-bit ripple carry adder. To construct the compact online testable full adder as well as an online testable ripple carry adder, we have proposed a parity preserving adder gate namely CFTFA gate that optimizes the total numbers of gates, garbage outputs, quantum cost and constant inputs of the circuitry. We show that,...
A new method of high level test generation based on the concept of test groups to prove the correctness of a part of system functionality is proposed. High-level faults of any multiplicity are assumed to be present in the system, however, there will be no need to enumerate them. Unlike the known approaches, we do not target the faults as test objectives. The goal of using the test groups is to extend...
Motor drives are used in a wide range of industrial applications, many of which impose high reliability demands on the electronics used in them. Moreover, the environmental conditions in industrial applications may vary a lot and therefore reliability studies for the motor drives are essential. In this study the reliability of a low voltage motor drive was studied with two different temperature cycling...
Decomposition of the time reversal operator (DORT) recently adopted to wiring fault detection and localization presented effectual results when dealing with a single soft fault along with complex network configurations. On the other hand, it failed in handling the task of locating multiple faults within even simple ones. In this paper, we propose an enhanced version of the standard DORT technique...
With process scaling and the adoption of post-CMOS technologies, permanent faults are becoming a fundamental problem. Circuits containing defects are either discarded (reducing yield) or partially disabled (reducing performance). In this paper, we propose a general approach using supervised and discriminative learning techniques to compensate for the effect of permanent faults on a circuit's output...
Due to the increasing usage of embedded instruments in many electronic devices, new solutions to effectively access these instruments appeared, including the new IEEE 1687 standard. The approach supported by IEEE 1687 allows a flexible access to embedded instruments through the Boundary Scan interface. The IEEE 1687 network includes a set of reconfigurable scan chains. This paper addresses the issue...
IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (Cps). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of...
As technology scales down, the density of SRAM devices increases drastically, and their storage capacity grows at the same time. Moreover, SRAMs become more prone to physical defects in each technology node, which therefore increases the need of effective tests with high fault coverage. It has been shown that resistive-bridging defects induce coupling faults that may increase defective parts per million...
In recent years, various high-level test synthesis methods for data paths have been proposed for the improvement in design productivity and test cost reduction. Most of the approaches assume that controllers and data paths are isolated from each other, and hence the hardware overhead becomes large. On the other hand, the approach without separation of a controller and a data path usually decreases...
The increasing power consumption during the chip testing process has become the bottleneck of chip production and testing for micro-nano VLSI circuits. Numerous low power design-for-testability (DfT) techniques have been proposed to deal with the test power problem, and segmented scan method was shown to be an efficient solution. We propose a new poweraware scan segment architecture, which can accurately...
DC circuit breakers are essential components in the protection of multi-terminal and meshed DC grids. So far, no practical application of HVDC circuit breakers is known and intense research is being carried out regarding various concepts, practical realization and ultimately testing of such devices. In the present contribution, several breaker concepts, based on the hybrid method of DC fault current...
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