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Scan test which is one of the useful design for testability techniques is effective for LSIs including cryptographic circuit. It can observe and control the internal states of the circuit under test by using scan chain. However, scan chain presents a significant security risk of information leakage for scan-based attacks which retrieves secret keys of cryptographic LSIs. In this paper, a secure scan...
This paper presents a proposal to express JTAG as an asynchronous packet-based protocol while maintaining full backward compatibility. This allows JTAG to transparently access remote units over high-bandwidth functional connections, a feature of special interest, for instance, in the environment of wireless telecommunication infrastructure and interfaces like CPRI or IP.
This paper, as a case study and tutorial, discusses testing methods for general PLL features and their operating margin. These methods can be applied all for analog-, digital- and PW-PLLs. There are various kinds of on-chip measurement macros which can be applied for the PLL testing, and for the direction toward digitally assisted analog circuit testing, it is shown that a digitally controlled variable...
Today, at-speed test cost comprises a majority of the total test cost of a design. This derives from the fact that if the design has numerous data transfers between clock domains, we must generate test patterns for all of the synchronous data transfers to guarantee high reliability. Conventionally, at-speed test patterns are generated for each of the transfers separately. In order to reduce at-speed...
In this paper, we present, for the 1-bit/stage pipelined ADC, a self-characterization technique that quantifies the per-stage capacitor ratio and comparator offset - the two main nonlinearity sources. In the proposed loop test, two adjacent pipelined stages are reconfigured to form a loop. Then, DC test stimuli are applied. The capacitor ratio and comparator offset of the stage under test are derived...
This paper proposes a novel scheme to manage capture power in a pinpoint manner for achieving guaranteed capture power safety, improved small-delay test capability, and minimal test cost impact in at-speed scan test generation. First, switching activity around each long path sensitized by a test vector is checked to characterize it as hot (with excessively-high switching activity), warm (with normal/functional...
High peak power consumption during test may lead to yield loss. On the other hand, reducing too much test power may lead to test escape. In order to overcome this problem, test power has to mimic the power consumed during functional mode, being as high as possible but not crossing the frontier of over-consumption. Measuring power consumption is a very time consuming activity, therefore many works...
Scan based at-speed testing has become mandatory in industry to detect delay defects today in order to maintain test quality and reduce test cost. However, the effects of power supply droop during test application often introduce timing uncertainty, such as clock stretch and additional gate delay. It leads to false failure and test escape during test and makes the application of the at-speed scan...
Unified Modeling language (UML) is a high level modeling language which comes with new approaches in the modeling, design, documentation, & testing of embedded systems. Systems like small satellites need extensive design, documentation and testing complexities, therefore all the subsystems need to be designed in such a way that the final system fulfills its design requirements and functionality...
High-speed digital LSIs such as CPU, graphic processing LSI, and System-on-a-chip, are indispensable for all the today's consumer electrics. However, such today's high performance LSIs require careful debugging for timing related errors and high quality delay fault testing for the dependability. This paper presents time-multiplexed on-chip delay measurement to realize fast and high quality timing...
Scan-chains are test infrastructures included in a circuit for providing high fault coverage. However, they can be exploited by an attacker as a side-channel in the case of a cryptographic application like AES. Test Compression and thereafter X-tolerance and X-masking over it, which reduce test effort without compromising on testability, can help in counteracting scan-based attacks. This work focuses...
In recent years, liquid crystal displays (LCD) have almost completely replaced older technologies such as cathode ray tube (CRT) displays in many industrial, commercial, aerospace, and military applications due to their increased efficiency, decreased weight, and smaller size. Likewise, the technology used to transmit video signals to LCD displays has evolved from analog standards such as the National...
Deterministic replay debugging is a technique aimed at finding and debugging software failures occurring in field operation that are usually hard to reproduce. With deterministic replay debugging a software run is recorded, so that it can be reproduced deterministically in a debugger. While deterministic replay debugging is capable of reproducing a failure, in practice, especially in the case of a...
We present the concept of runnable virtual nodes (RVNs) as means to achieve predictable integration and temporal error-containment of real-time software components. An RVN exploits the latest techniques for hierarchical scheduling and is intended as a coarse-grained component for single-node deployment, that provides functional and temporal isolations with respect to its environment. It uses a two-level...
The recently proposed asynchronous nanowire crossbar architecture is envisioned to enhance the manufacturability and robustness of nanowire crossbar-based configurable digital circuits by removing various timing-related failure modes. Even though the proposed clock-free nanowire crossbar architecture has numerous technical merits over its clocked counterparts, it is still subject to high defect rates...
Testing real-time systems is a non-trivial validation task, especially after adding time as a new dimension to its complexity. In previous research, we introduced a 'priority-based' approach which tested the logical and timing behaviour of real-time systems modelled formally as UPPAAL Timed Automata (UTA). In this paper, we validate the 'priority-based' approach with a comparison to four well-known...
Testing multi-threaded programs is hard due to the state explosion problem arising from the different interleavings of concurrent operations. The dynamic partial order reduction (DPOR) algorithm by Flanagan and Godefroid is one solution to reducing this problem. We present a modification to this algorithm that allows it to exploit the commutativity of read operations and provide further reduction...
For the complicated digital bus device testing, there are two approaches: dedicated bus instrument and general-purpose digital IO instrument. The dedicated bus testers provide more advanced capability including exercising the bus, injecting errors, fully characterizing specification compliance for design validating and verification phase. This paper presents a modular solution based on the general-purpose...
This paper describes the architecture (circuit design) and principles of operation of sigma-delta Sigma-Delta time-to-digital converters (TDC) for high-speed I/O interface circuit test applications, they offer good accuracy with short test times. In particular, we describe multi-bit TDC architectures for fast testing. However, mismatches among delay cells in delay lines degrade the linearity...
Resistive open fault (ROF) represents common manufacturing defects causing extra delays and reliability risks in affected circuits. ROF behavior is sensitive to the supply voltage and the resistance of open (RO). Modeling this fault behavior and detectability with the supply voltage helps in distinguishing between faults as well as testing of multi-voltage designs. While previous ROF models did not...
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