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An electronic design and evaluation tool for quantum circuit design is presented. It allows easy implementation of quantum algorithms based on the circuit model of quantum computation. The layout of an ideal circuit network can be designed in the logical layer and then automatically get converted into an encoded form closer to the physical layer. The possibility to select and apply the desired quantum...
This paper investigates the impact of inter- and intra-die variations on binary and high-radix adders that adopt the borrow-save encoding. High-radix adders have been employed for the recoding of multipliers and for determining quotient and root digits in iterative division and square-root algorithms. These adders have been found to outperform conventional ripple-carry and carry-skip adders in certain...
On-chip coding provides a remarkable potential to improve the energy efficiency of on-chip interconnects. However, the logic design of the encoder/decoder faces a main challenge: the area and power overhead should be minimal while, at the same time, decodability has to be guaranteed. To address these problems, we propose the concept of approximate coding, where the coding function is partially specified...
Unknown values emerge during the design and test generation process as well as during later test application and system operation. They adversely affect the test quality by reducing the controllability and observability of internal circuit structures - resulting in a loss of fault coverage. To handle unknown values, conventional test generation algorithms as used in state-of-the-art commercial tools,...
This paper is based on cyclic redundancy check based encoding scheme. High throughput and high speed hardware for Golay code encoder and decoder could be useful in digital communication system. In this paper, a new algorithm has been proposed for CRC based encoding scheme, which devoid of any linear feedback shift registers (LFSR). In addition, efficient architectures have been proposed for both Golay...
Usually, test pattern decompressors with dynamic reseeding are reset before starting a new test pattern decoding. The first few scan chain slices are then filled with test vectors that have lower decodability as the number of free variables is limited by the test access mechanism bandwidth. We have found that it is possible to increase the number of free variables in the equations describing the care...
This paper focuses Two's complement multipliers with Shortest Bit-size were used without any increase in the delay of the partial product stage. This was done by reducing one row the maximum height of the partial product array generated by a radix-4 Modified Booth multiplier, this reduction may allow for a faster compression of the partial product array and regular layout. By using this method, it...
Continuous technology scaling makes NAND flash cells much denser. As a result, NAND flash is becoming more prone to various interference errors. Due to the hardware circuit design mechanisms of NAND flash, retention errors have been recognized as the most dominant errors, which affect the data reliability and flash lifetime. Furthermore, after experiencing a large number of programm/erase (P/E) cycles,...
Stochastic logic performs computation on data represented by random bit streams. The representation allows complex arithmetic to be performed with very simple logic, but it suffers from high latency and poor precision. Furthermore, the results are always somewhat inaccurate due to random fluctuations. The random or pseudorandom sources required to generate the representation are costly, consuming...
This paper presents an efficient DNN design with stochastic computing. Observing that directly adopting stochastic computing to DNN has some challenges including random error fluctuation, range limitation, and overhead in accumulation, we address these problems by removing near-zero weights, applying weight-scaling, and integrating the activation function with the accumulator. The approach allows...
There are situations (e.g. for reverse engineering or formal verification) circuit designers would need to extract complicated arithmetic circuitry deeply embedded inside a fully synthesized (or manually touched) million-gate flattened netlist without the knowing of module boundary and IO positions. Besides not knowing the IO and boundary, a formal verification task like comparing two netlists implementing...
IBM's Spoken Web Service enables illiterate and disadvantaged communities in the developing world to create and access VoiceSites over the phone. A pilot study was used to examine the adoption of this service by a community of farmers in rural Gujarat, India. Data analysis carried out using the principles of grounded theory helped us identify the factors responsible for the adoption of the service...
Unknown (X) values in a design introduce pessimism in conventional test generation algorithms, which results in a loss of fault coverage. This pessimism is reduced by a more accurate modeling and analysis. Unfortunately, accurate analysis techniques highly increase runtime and limit scalability. One promising technique to prevent high runtimes while still providing high accuracy is the use of restricted...
Stochastic circuits provide very high efficiency in terms of gate area and power consumption compared with conventional binary logic. However, they require random bit streams generated by stochastic number generators (SNGs), which account for a significant portion of area and energy offsetting their merits. In this paper, we propose a new SNG that significantly reduces area and energy while improving...
Flash type analog to digital converters (ADCs) have the highest speed amongst all the available ADCs because of their parallel architecture. The comparator outputs in a flash ADC are in the so-called ‘thermometer code’ form. Because of device mismatch, clock jitter, offset voltage and metastability problems prevalent in a flash ADC, it suffers from bubble or sparkle error problem. This thus leads...
We present the design and organization of an homogeneous asynchronous bit-level array based on Null Convention Logic. A bit element (bel) array represents a bit-level hybrid processor that exhibits both Spatial and Temporal computing characteristics. The bit elements are organized in a 2D grid, with eight-way connectivity. Programs represented as Directed Acyclic Graphs can be mapped to the array...
Ultra wide band communication systems extensively rely on low resolution and Giga samples per second data converters. Moreover, technology scaling beyond 90 nm drastically complicates the design of the communication systems. With the increasing complexity in communication systems, greater demand for higher performance and more conversion speed while maintaining power consumption at a reasonable level...
The development of low power systems gained significant importance and impressive progress has been made in this domain in the recent years. However, despite more efficient circuit technologies (made possible e.g. by the ongoing miniaturization of integrated circuits) as well as improvements in battery technology, also the way how computations are logically performed may have an effect on the required...
Increasing rates of soft errors at the nanometer scale require effective fault tolerant solutions. Recently, a finite state machine (FSM) based fault tolerance technique for sequential circuits has been proposed. The technique is based on protecting few states with high probability of occurrence by adding equivalent redundant states. The resulting state assignment solution satisfies the fault tolerance...
Reversible circuit is the one which prevents information loss by reversible logical operations and reduces energy consumption. For this reason, the synthesis of these circuits, particularly in nanotechnology, was addressed by researchers. Reversible circuits are created through connection of reversible gates and feedback and fan-out are not allowed in their outputs. These features led to different...
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