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This paper describes the design of a bandgap reference for driving low impedance, simulated in 0.35 mum CMOS technology. The circuit generates a reference voltage of 1.23 V and has a temperature coefficient of 0.02 mV/K at 27degC. It can operate with supply voltages between 2.5 V and 6 V and between 0degC and 100degC. It has a PSRR of 41 dB under normal operating conditions. This circuit works in...
A current mirror (CM) is reconfigured based on self cascode (SC) arrangement, useful for low voltage (LV) analog and mixed mode circuits. The CM uses 4 MOSFETs, has high input and output swing, operating at plusmn0.5 V supply. Further, a novel CMOS CCII has been revisited and implemented using this CM for sourcing the mirrored current into a high impedance output node. P-spice simulations confirm...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
A 65 nm CMOS, 60 GHz fully integrated power amplifier (PA) from STMicroelectronics has been designed for low cost Wireless Personal Area Network (WPAN). It has been optimized to deliver the maximum linear output power (OCP1) without using parallel amplification topology. The simulated OCP1 is equal to 8.9 dBm with a gain of 8 dB. To obtain good performances and consume an ultra compact area of silicon,...
Regular Current-Steering D/A Converters (CS-DACs) using high-swing cascode current-source structures fail to operate with very-low supply voltages. In this paper, body- driven enhanced-impedance current cells have been employed to satisfy required characteristics of CS-DAC in low headroom voltage. In this technique, a body-driven amplifier increases the output impedance of a cascode current source...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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