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This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
This article shows the design of an on-chip CMOS implementation for an alternative topology to classic switching DC-DC power converters. In the presented technique, an auxiliary linear regulator is used to cancel the output voltage ripple and provides fast responses for load and line variations. On the other hand, a switching converter, connected in parallel, allows supplying almost the whole output...
The paper describes structural design of a full (complete) low dropout (LDO) voltage regulator. This LDO is using the following basic subcircuits: bandgap reference (BGR), folded-cascode current operational amplifier (COA), and bias circuit. The regulator is divided in three main blocks, namely, a sub-regulator generating power supply voltage for the BGR, a scaling amplifier providing convenient reference...
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