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The various speed limiting influences in conventional MTL devices are investigated. Even with thin epitaxy, charge storage in the npn part remains the main speed detractor. Hence, the npn part should be improved firstly, e.g. using polysilicon techniques.
The problem of designing asynchronous circuits where the changes in binary input signals occur independently of one another is discussed. If several input changes occur within some interval δ1, the circuit behaves as though the changes were simultaneous. If consecutive changes are spaced by intervals exceeding some longer interval δ2 then the circuit reacts as though a sequence of single changes had...
It is generally recognized that asynchronous operation of logic networks offers specific advantages over synchronous operation controlled by a central clock when the network is subject to large or widely varying inter-module propagation delays. In this paper we characterize several previously described techniques for achieving asynchronous operation by a single model. Essential to the model is the...
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