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A 100μW, 13bit ADC used for sensor array applications is presented in this paper. The ADC employs an extended counting architecture in which the residual error from a first-order incremental ΣΔ modulator is encoded by a cyclic ADC to achieve high accuracy at a relatively high speed. Hardware reuse technique is utilized for low power consumption and small silicon area. The prototype ADC is implemented...
This paper presents a synthesizable cyclic Vernier time-to-digital converter (TDC) with digitally controlled oscillators (DCOs). All functional blocks in the TDC are implemented with digital standard cells and placed-and-routed (PAR) by automatic design tools; thus, the TDC is portable and scalable to other process technologies. The effect of PAR mismatch is characterized in the post-layout simulation...
This paper presents a high-throughput asynchronous protocol converter between two-phase communication links and four-phase pipelined routers for asynchronous Network-on-Chip. In the proposed protocol converter, two-phase input and output signals are encoded to and decoded from the four-phase signals, respectively, by using two controllers which are attached to the router. Since the two controls are...
In this paper, an integrated DC-DC (Buck) converter is presented. The Buck converter has two modes of operation. The continuous mode is used for heavy loads, and the pulse-skipping modulation (PSM) mode is used for light loads. To optimize the Buck converter efficiency in PSM mode, an ON-time control loop is utilized. Short-circuit and over-temperature protection schemes are used to improve the design...
Three freewheel duration adjustment circuits based on the principle of phase-lock loop are proposed to enhance the efficiency of single-inductor dual-output (SI-DO) switching converters. The SI-DO converter works in pseudo-continuous conduction mode and uses charge control with a single-charge successive-discharge scheme. The first circuit defines a constant freewheel time (TFW); the second uses the...
This paper describes a readout channel suitable for infrared and terahertz bolometric sensors arrays where the signal integration is performed simultaneously with the analog-to-digital conversion in a columnwise architecture. By exploiting the need of an integrator both in conventional IR readout channels and incremental converters, the proposed circuit implements a 5-bit continuous-time incremental...
A compact resistor-less current detector that protects linear regulators against overcurrent is proposed. The circuit suits converters with either p- or n-channel pass-device, for different dropout voltages. The ratio between detection threshold ITH and a reference current IREF depends only on transistor geometry scaling, making the detector robust to process and temperature (PT) spread. As part of...
A monolithic step-up dc-dc converter with on-chip spiral inductors is designed and simulated to determine its feasibility for low-power portable applications. The converter is operated at a relatively high frequency of 600 MHz to reduce passive component sizes. Quality factor limitations of on-chip inductors are mitigated without increasing the area by implementing multiple spirals on different layers...
In this paper, we present new systematic method for the design of an analog PID controller, applied to the voltage-mode step-down (buck) DC/DC converters. The method relies on the specification of trajectory of the load transient response. Particularly, we are interested to design a controller limiting the voltage under/overshoot to its lowest possible value. It is shown that this lowest possible...
It is well known that the performance of current-steering D/A converters (DACs) is affected by parasitic effects such as static device mismatch and dynamic timing mismatch. Typically, this results into about 10-bit peak performance. To increase this number, the designer has two options: either use a very large silicon area to obtain better matching, or alternatively use a (sophisticated) calibration...
This paper presents a high resolution two-step gated-ring oscillator (TSGRO) time-to-digital converter (TDC) in an all digital phase-locked loop (ADPLL). TSGRO-TDC consists of a coarse step and a fine step gated-ring oscillator (GRO) TDC to achieve a high resolution. An edge aligner is used in the fine step GRO-TDC to enhance a first-order noise shaping property. A meta-stability free selection logic...
This paper presents a low voltage CMOS full-wave rectifier for wirelessly powered devices. By using a simple comparator-controlled switch, the lowest input voltage amplitude can be reduced to 0.7V when using a standard CMOS 0.18μm process. With only one comparator, the proposed design dramatically reduces the production cost. In combination with unbalanced transistor scale, the proposed rectifier...
This paper proposes a fully integrated asynchronous step-down switched capacitor DC-DC conversion structure. The circuit uses a fully digital asynchronous state machine as the heart of the control circuitry. To minimize the switching losses, the asynchronous controller scales the switching frequency of the converter according to the load. It also turns on additional parallel switches when needed....
A novel analog-to-digital converter (ADC) architecture, named domino architecture, is introduced. The proposed idea can be taken as the continuous-time counterpart of SAR ADCs, and at the same time it resembles a series version of flash ADCs being implemented with much less circuit complexity and chip area. The basic idea is then pipelined in order to speed up the conversion process, leading in a...
A compact (0.01mm2) coarse-fine time-to-digital converter (TDC) in 40nm LP CMOS achieves 5.5ps resolution using parallel delay lines. A 6fJ/conversion step efficiency is achieved thanks to efficient residue calculation. A 0.8LSB single-shot precision and low DNL are reached thanks to simple calibration which is possible in fractional-N PLLs. Further, metastability avoidance and digital error correction...
The design and modeling of a high performance SAR ADC with non-lumped capacitor array is presented in the paper. Based on this mode, the operation method that diminishes nonlinearity parasitical capacitor in the interior DAC is developed to design a 12-bit SAR ADC. An innovative C-carry architecture aimed at the traditional lumped capacitors is discussed. The new capacitor array is composed of identical...
In this paper we present low-voltage multiple-valued gates. The low voltage gates may operate at a supply voltage below 250mV. We utilize the ultra low voltage CMOS logic style [1][2] to implement simple multiple-valued circuits. The radix used is determined by the supply voltage and is limited to 4 for a supply voltage equal to 250mV . Simulated data presented are valid for a ST 90nm CMOS process.
A digital calibration technique based on the split-ADC is proposed to correct linear gain errors in a 10-bit pipelined A/D converter, which allows the use of low-gain amplifiers in conversion stages. Fabricated in a 0.35-μm CMOS technology, the core area of the ADC occupies 1.64 mm2. The opamp-sharing technique helps to reduce the core power consumption to 45 mW from a 3-V supply voltage at 50 MS/s...
An integrating analog-to-digital data converter (ADC) with variable resolution for radio-controlled servo motor applications is presented. A voltage-to-pulse converter VPC by using a pulse-controlled circuit is presented against the process variations. This integrating ADC is fabricated in a 0.18μm CMOS process and its resolution bit is reconfigurable from six to ten bits with the sampling rate from...
This paper presents a 12-bit fully differential successive approximation register analog-to-digital converter (ADC) operating at 2MS/s and designed for an optoelectronic range sensor as a system-on-chip device. The realized ADC uses several improvements to lower the power consumption to 10mW at 5V power supply and, at the same time, to increase the conversion rate up to the limits offered by the used...
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