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This paper demonstrates a fully integrated frequency shift keying (FSK) receiver built with standard cells in .18μm CMOS without any off-chip components. Building a receiver with standard cells dictates that an inverter-based ring oscillator, rather than an LC oscillator, will be used for LO generation. This approach reduces the effort required when redesigning the receiver in a different process...
This paper presents a 0.5 V pseudo fully differential CMOS op-amp with rail-to-rail input/output swing. The circuit is designed based on class AB input and output stages. In the design, quasi FGMOS transistors are employed. The proposed amplifier is designed using 0.18 μm CMOS technology, and the simulation results show rail-to-rail input and output swings. The open-loop gain and gain-bandwidth product...
A 0.18 μm CMOS RF receiver front-end applying in DSRC systems is presented in this paper. The proposed receiver front-end includes the current-reused LNA, the folded Giber cell mixer, and the Colpitts VCO. Also, this paper presents the design methodology and application of the transformer balun for RFIC. The measured results of the proposed receiver front-end show the input return loss of 30.5 dB,...
This paper presents the design of a 2-16 GHz ultra wide band low noise amplifier (UWB LNA). The proposed LNA has a gain of 11.5 ± 0.85 dB with NF less than 2.82 dB. Good input and output impedance matching, good isolation and linearity are achieved over the operating frequency band. The proposed UWB LNA consumes 18.14 mW of power from 1.8 V supply. This UWB LNA is designed and simulated in 0.18 μm...
A lag-free CMOS image sensor (CIS) with Constant-Residue Reset (CRR) operation is presented in this paper. It effectively eliminates image lag effect caused by the channel doping profile variation of transfer transistor and non-optimized pixel layout in the 4T-pixel. A prototype 160×120 CMOS imager has been designed and fabricated in 0.18um 1P4M CIS process. The experimental results demonstrated that...
This paper presents a decoupling capacitance boosting method for on-chip resonant supply noise reduction for DVS systems. The switching controls of decoupling capacitors depending on the supply noise states achieve an effective noise reduction and fast settling time simultaneously compared with the conventional passive decoupling capacitors. The measurement results of a test chip fabricated in a 0...
The H.264/AVC intra-frame codec is widely used to compress image/video data for applications like Digital Still Camera (DSC), Digital Video Camera (DVC), Television Studio Broadcast, and Surveillance video. Intra-prediction is one of the top 3 compute-intensive processing functions in the H.264/AVC baseline decoder and, therefore, consumes significant number of compute cycles a processor. In this...
Based on the transceiver architecture of WLAN 802.11a, the frequency plan of the RF transceiver is accomplished. A PLL (phase-locked loop)-type frequency synthesizer used for the system has been implemented in the standard 0.18-μm mixed-signal and RF 1P6M CMOS technology of SMIC. It integrates a VCO, a dual-modulus prescaler, PFD, a charge pump, a control logic, various digital counters and digital...
This paper presents a 1.6 mW, 20 MS/s DAC with 0.33 pJ/conversion-step figure-of-merit, effective number of bits exceeding 7.9 and 0.40 mm2 total chip area. A new variety of the non-binary series allowed design of the switched-capacitor charge pump array, with switched capacitance 7.3 pF, maximum to minimum capacitance ratio 7.2 and 7 matched capacitors, resulting in compact DAC layout. The proposed...
In this paper, A Software-Defined Radio (SDR) RF front-end is presented that contains LNA, mixers, VGAs, and frequency synthesizer, supporting various wireless communication standards in 0.1-2 GHz while guaranteeing a power/performance trade-off at any time. The circuit is fabricated in a 0.18 μm RF CMOS technology with 1.8 V supply voltage. Simulated result shows that the receive path achieves a...
This paper presents a Built-in Self-Test (BIST) scheme and its implementation for a current-mode R-2R ladder Digital-to-Analog Converter (DAC). The technique is based on the resistance match of the R-2R ladder in DAC. With the extra Design for Testability (DFT) circuits, test constant current follows into two resistance-matched branches, and the voltage drops on two branches of the resistor ladder...
In this paper, a low voltage low power (LPLV) current output stage (COS) with high CMRR is proposed. A novel common mode feedback (CMFB) technique is exploited to provide high CMRR. That is done by summing the main common mode signal and its opposite polarity one which provides over 112 dB of CMRR in 0.18 μm CMOS technology of TSMC. The circuit operates with very low supply voltages of ±0.5 V and...
A fully differential feedback third-order continuous-time sigma-delta modulator suitable for Mega Hertz wireless communication is presented. Some design optimizations mainly regarding power consumption are demonstrated. The proposed single-bit modulator clocked at 128 MHz achieves 2 MHz signal bandwidth, 11 bits of resolution, 68 dB signal-to-noise ratio and 66 dB dynamic range. Designed in 0.18 μm...
In this paper, a broadband CMOS differential LNA for DC~2 GHz software defined radio is proposed. The channel thermal noise and the flicker noise of input MOSFET is canceled by exploiting a noise-canceling technique. A lower noise figure and an excellent wide-band input matching can be achieved at the same time. Moreover, the distortions introduced by input MOSFET can be partly cancelled using the...
A new switch control method for a capacitive DAC architecture has been presented. This has been implemented to make a successive approximation register (SAR) ADC more energy efficient. By splitting the capacitor array into two equal halves and using a unity gain buffer, the proposed architecture reduces the switching energy by 97 percent compared to the conventional switching method. The proposed...
In this paper, a prototype delta-sigma ADC is implemented in a 0.18μm 2P5M CMOS process. The input signal sampling capacitors are shared with the front-end DAC capacitors. The sampling frequency is 50MHz and oversampling ratio is 24. The out-of-band peaking is deliberately set to help the stability and to allow larger input signals to be processed by the loop. This modulator achieves 78.2dB peak SNDR...
The high channel count of many modern communication systems increasingly requires high-performance ADCs that consume very little power. The 16b pipeline ADC described here achieves 77.6dBFS SNR, 77.6dBFS SNDR and 95dBc SFDR at 80MS/S with a 10MHz input. With a 200MHz input, the ADC achieves 71.0dBFS SNR, 69.4dBFS SNDR and 81dBc SFDR. The complete ADC including reference, clock, and digital circuitry...
Conventional cameras capture 2D photographs at a single plane of focus. Acquisition of a 3D photograph with multiple planes of focus typically requires scanning the focus of a single camera, or using arrays of cameras or lenses. This paper demonstrates a 150kpixel image sensor, which captures 3D scenes. The chip is manufactured in commodity 0.18μm CMOS and requires only a single convex lens at a fixed...
A wide band Low Noise Amplifier (LNA) in 0.18 μm CMOS technology, employing noise cancellation and current reuse, which receives different wireless standards over a frequency range of 900 MHz to 6 GHz, is designed, analyzed and simulated. The LNA provides a power gain of 17.5 dB with a power dissipation of 13.7 mW, and a noise figure (NF) of 2.6 to 3.5 dB over a bandwidth of 0.9 GHz to 6 GHz.
This paper presents the design of a low-power single-full-band (3.1-10.6 GHz) noncarrier impulse-radio ultra-wideband (UWB) transmitter (TX) implemented in a commercial 0.18-μm CMOS technology. This UWB TX features fifth-order Gaussian derivative pulse shaping, integrated binary phase-shift keying modulation and 2.5-kV whole-chip electrostatic discharge (ESD) protection. Measurement shows full function...
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