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At-speed scan testing for intra-clock and inter-clock transition delay faults in a SOC design with multiple clock domains is an important and challenging issue. Current practice in industry usually applies a test scheme targeted on intra-clock transition fault delay testing (i.e., intra testing). In this paper a test scheme targeting both intra-clock and inter-clock domains for transition delay fault...
This article introduced a design principles and implementation method of a high resolution programmable digital delay generator. It described the system's composition in hardware and software view. This system is composed of deserializer MAX3885, high-speed clock generator AD9517-1, DDR2 SDRAM, serializer and USB2.0 Controller. Paper described FPGA software design methods includes DDR2 SDRAM controller...
This paper presents a new at-speed logic built-in self-test (BIST) architecture using staggered launch-on-shift (LOS) for testing a scan-based BIST design containing asynchronous clock domains. The proposed approach can detect inter-clock-domain structural faults and intra-clock-domain delay and structural faults in the BIST design. This solves the long-standing problem of using the conventional one-hot...
The concept of merging some 1-bit flip-flops into a multi-bit flip-flop is applied to reduce dynamic clock power and decrease the total flip-flop area in a synchronous design. To acquire these advantages, the design must be guaranteed to satisfy certain physical constraints in the merging process. In this paper, given a set of 1-bit flip-flops with the input and output timing constraints, the area...
There is a growing demand for high-performance, low-power systems, particularly in portable devices. New approaches to design are needed in technologies with feature sizes of 90 nm and below to reduce leakage power and to deal with process variations, which force designers to use increasingly conservative delay estimations. This paper presents a variable clock generator for a conventionally-designed...
This paper describes the experience from the world first installation of Smart High Voltage substation with IEC 61850 Process Bus where IEEE 1588 Time Synchronization and dynamic multicast filtering have been used. IEC 61850 is one the 30 standards identified by NIST as key elements for achieving interoperability in the Smart Grid. This paper describes the experience from a high voltage substation...
ICx Radiation, Inc. has implemented a novel timing method for use in a Compton telescope that is capable of nanosecond timing resolution. A critical task in Compton telescope design is to minimize the timing variance between detectors in a large array in order to reduce the background. The voxelSPEC has been developed to combine precise timing with pulse processing electronics in a single device,...
This paper analyzes high-speed source-synchronous network-on-chip data links in terms of yield loss due to delay variations. We show that statistical process variations can significantly reduce yield at high data rates and high bus widths. An on-chip delay calibration architecture for individual calibration of rise and fall delay times is proposed and analyzed on system level using Monte Carlo simulations...
An algorithm for implementing higher layer synchronization in ECMA-368 networks is being developed within the framework of the EUWB research and development project. In this paper, we adapt three synchronization algorithms used in wireless sensor networks to suit an Ultra Wideband (UWB) network and evaluate their performance in order to determine the best algorithm for a video streaming application...
Using the Precision Time Protocol (PTP) specified by the IEEE 1588 standard, synchronization of distributed clocks is achieved by propagating the timing information of a preselected master clock throughout the entire network. Based on this directly or indirectly obtained noisy timing information, each slave clock tries to follow as closely as possible the master time. This paper formulates the PTP...
Synchronization interfaces in a network-on-chip (NoC) are becoming vulnerable points that need to be safeguarded against link delay variations and signal misalignments. This paper addresses the challenge of designing a process variation and layout mismatch tolerant link for GALS NoCs by implementing a self-calibration mechanism. A variation detector senses the variability-induced misalignment between...
This study proposes a output loading effect insensitive and high precision clock synchronization (HPCS) circuit which can accept variable duty cycle clock signal. This HPCS is capable of synchronizing the external clock and the internal clock in 3 clock cycles. By using three innovative techniques, the proposed HPCS can also reduce the clock skew between the external clock and the internal clock in...
Conversion from dc to the 10th Nyquist band is enabled in a SHA-less, 10-b, 100-MS/s pipelined ADC by digitally calibrating the clock skew in the 3.5-b front-end stage. Architectural redundancy of pipelined ADC is exploited to extract skew information from the first-stage residue output with two out-of-range comparators and some simple digital logic; a gradient-descent algorithm is used to adaptively...
In peer-to-peer (P2P) applications, a group of multiple peer processes (peers) are required to cooperate with each other. In this paper, we discuss a heterogeneous hybrid time group communication (HHT) protocol which takes advantage of the linear time (LT) and physical time (PT) to causally order messages in a scalable heterogeneous group. It depends on accuracy of each physical clock and minimum...
At present, an increasing number of distributed control systems are based on platforms made up of conventional PCs running open-source real-time operating systems. Often, the need arises in these systems to have networked devices supporting synchronized operations. In this paper, an inexpensive solution is introduced, described, implemented and evaluated that relies on standard software and protocols...
A duty cycle correction (DCC) circuit with deterministic clock insertion delay is presented. To neutralize the ambiguity of the DCC circuit insertion delay induced by the wide range of input clock duty cycle, a signal differentiating circuit at the input of the circuit is used which narrows the input duty cycle range to the circuit core. We achieved deterministic delay between rising edges of the...
This paper presents a master redundancy technique for improving the availability of synchronization in IEEE 1588. We propose a novel best master clock (BMC) algorithm to take account of link congestion between master and slave nodes. To determine the priority of master nodes, a BMC algorithm with a simple link congestion estimation based on a modified IEEE 1588 message sequence is used. The effectiveness...
Targeting the distribution of accurate frequency and time references across Packet Switched Networks (PSNs), the IEEE Std 1588™-2008 (a.k.a. 1588V2 or PTPV2) standard specifies network infrastructure components intended to reduce the impact of network elements located between the Grandmaster clock and Slave clocks. Also referred to as On-Path Supports (OPS), these PTPV2 build-in network components...
Packet delay variation (PDV) is a dominant source of noise in packet-based synchronization systems. To filter this type of noise, many clock recovery algorithms select packets based on the sample-minimum statistic of the network transit time. Although such a filter can be very effective in certain types of networks, there are just as many networks and background traffic patterns for which sample-minimum...
This paper presents a fast-lock wide-range all-digital delay locked loops (ADDLL) for mobile applications. The proposed open-loop architecture based on time-to-digital converter (TDC) has a lock time of 3~10 clock cycles. The multipath delay line is implemented to achieve high resolution in TDC. The frequency range selector is adopted for a wide-range operation. The ADDLL is implemented in a 0.18μm...
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