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A comma detection and word alignment circuit is proposed for a 6.25-Gb/s SerDes. In order to achieve a high speed, a new architecture of combined parallel and pipelined is employed. Based on the proposed structure, a high speed comma detector is implemented using 0.18im CMOS technology. Post simulation result indicates that the circuit can operates up to 770MHz with a power consumption of 10.8 mW...
At present, computer clock synchronization among computers is usually realized through hardware method. It always result in high cost and inconvenient in practice, also it can only use in small-scale net. However, the software method has the advantage of lower cost and better flex, and is appropriate for the miniature distributed network and dynamic measurement areas whose synchronization precision...
The TIGER-3 radar is being developed as an “all digital” radar with 20 integrated digital transceivers, each connected to a separate antenna. Accurate coordination of all 20 transceivers is essential for both generation of transmit signals and collection and merging of receive data to form a standard Su-perDARN data set. This paper proposes a clock synchronisation method to coordinate the operation...
As one of the key technologies in Ad hoc networks, clock synchronization is the prerequisite of important network functions. Main consideration in clock synchronization are the choice of global clock and the accuracy, in which the existing clock synchronization methods still suffer lack. In this paper, the network delay is measured in networking process, and the network nodes complete synchronization...
This paper discusses a method for synchronizing the clock of a client computer using messages transmitted over the Internet from a remote server. The design principles would also be appropriate for other types of connections between the client and the server, provided only that the delay through the network connecting them is symmetrical on the average.
In literature delay locked loop (DLL) architecture is used for synchronizing the on-chip serial interconnect transceivers instead of phase locked loops (PLL) due to increased stability and low jitter. In this paper, the design and implementation of a Mixed-Delay Locked Loop (DLL) for on-chip serial transceiver is carried out with a modified architecture, which takes less number of clock cycle for...
In this paper, an adaptive and robust monitoring approach for Wireless Sensor/Actuator Network (WSAN) environments is proposed. The main problem under investigation is the monitoring of the status of WSAN devices in an environment where the clocks of the devices are not well synchronized (asynchronous communication). The main contribution is the proposed adaptive virtual timer, for the server node,...
Clock synchronization is becoming an increasingly important characteristic of modern wide area monitoring and control systems such as the power grid. It provides an opportunity to coordinate control actions and measurement instants across hundreds of miles and numerous network topologies. Devices and networks have advanced to a point where synchronization across a wide area can be achieved within...
With the development of digital substation, the devices of the substation put forward higher demands on clock synchronization. The standard of the IEEE1588 provides a protocol that enables precise synchronization of clocks in measurement and control systems, and the precision of its network is sub-microsecond level which can satisfy the need of clock synchronization of the substation. This paper makes...
Evaluation of Wireless Sensor Networks is difficult. Due to lack of standard implementations, stringent time requirements and security enabled communications evaluation of WirelessHART networks is challenging. This makes it very hard to compare, evaluate and test WirelessHART networks even controlled environments. We propose a hybrid simulation framework that is tailored for the WirelessHART protocol...
A group of peers are required to cooperate with each other in distributed applications on P2P overlay networks. In order to realize a scalable P2P group, messages are causally ordered by taking advantage of linear time (LT) and physical time (PT) since message length is O(1) in this paper. In this paper, we newly discuss a multi-layered model to realize a scalable group. A group is hierarchically...
Design of cyber-physical systems poses new challenges. Design at the level of a whole cyber-physical system includes design issues such as formal and abstract specification, design space exploration, optimization, and verification. A particular challenge is the formal and abstract representation of whole cyber-physical systems including both physical and cyber components. The objective of this paper...
There are many test challenges generated from at-speed delay testing requirements. BIST circuit can help to solve traditionally slower AT E tester problems. In this paper, a double edge clipping technique is proposed for at-speed BIST testing. It differs from traditional circuit delay testing techniques by changing the clock rate using external ATE. This method uses lower-speed input clock frequency,...
This paper presents a time synchronization method based on the COMPASS code measurements in combination with two-way transfer ranging, which results the clock offset between COMPASS GEO satellite and the ground station. The clock offset of COMPASS G3 satellite on board is computed by using the data observed on October 2010. In order to verify the accuracy of this method, the results are compared with...
Modern robotic systems are composed of many distributed processes sharing a common communications infrastructure. High bandwidth sensor data is often collected on one computer and served to many consumers. It is vital that every device on the network agrees on how time is measured. If not, sensor data may be at best inconsistent and at worst useless. Typical clocks in consumer grade PCs are highly...
The goal is to distribute UTC(CH) in a remote location via TCP/IP. The MC (Master Clock) is locked to UTC(CH) via a combination of IRIG-B and 1-PPS signals. The SC (Slave Clock) is controlled by a PI control loop that tracks the MC. The SC-MC clock offset and the transmission delay are estimated simultaneously by means of a TW (Two-Way) comparison process similar to NTP but based on TCP/IP.
This paper describes the architecture and design of high-speed clock recovery circuit for burst-mode applications. Since the proposed circuit is non-PLL-type and designed in fully digital style, it can provide faster acquisition time, better scalability and portability compared to PLL-type or analog style clock recovery circuits. The proposed circuit recovers output clock for every transition of input...
The finite state machine (FSM) needed for the low power system pulse frequency modulated (PFM) mode in a buck converter is usually asynchronous because the fast clock needed for a synchronous FSM consumes too much power, or is maybe even not available. However, the implementation, verification and testing of a asynchronous FSM is complicated compared to an synchronous one. This paper presents a concept...
Recently, the maximum likelihood estimator (MLE) and Cramer-Rao Lower Bound (CRLB) were proposed with the goal of maximizing and assessing the synchronization accuracy in wireless sensor networks (WSNs). Because the network delays may assume any distribution and the performance of MLE is quite sensitive to the distribution of network delays, designing clock synchronization algorithms that are robust...
The effect of process variations on the clock skew in three dimensional (3-D) circuits with multiple clock domains is investigated. In 3-D ICs, the combined effect of inter-die and intra-die process variations should be considered in the design of clock distribution networks. A statistical clock skew model incorporating spatially correlated intra-die process variations is employed to describe this...
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