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We present a methodology for algorithmic generation of test signals for thedetection and diagnosis of a variety of short and open-circuit defects in analogcircuits. Prior algorithms have focused on test generation for known short oropen defect values. This places the burden of failure coverage on accurateanalysis of observed defects in known failed parts at high cost. In this work, we optimize the...
In this paper, we show how two key techniques in the testing and verification areas - namely mutation testing and assertion based verification (ABV) - can be combined in a novel way to help improve the effectiveness of verifying design correctness. Through assertion based test generation, multiple mutated designs and their test sequences are concurrently simulated using a GPU, in order to determine...
Iterative scan diagnosis is often needed for both the first silicon and the hard-to-diagnose chips. The chips in question are extracted from wafers and re-tested on a debug platform to arrive at a reasonable number of probable defect candidates that can be physically analyzed. This requires a large setup time and multiple iterations of deterministic diagnostic test pattern generation and application...
An unconventional software testing method, fault injection based on fault model, is enhanced to improve the software reliability testing and measurements. Dynamic fault models for injecting faults through software are investigated and reported in this paper including memory faults, CPU faults and communication fault models. Dynamic fault models can be used to simulate influences which are caused by...
The phenomenon of high availability (HA) is of vital importance in cloud architecture. This paper proposes an HA verification framework, called HAVerifier, for OpenStack, a popular open source cloud platform. Fault injection technology has been adopted to verify the system's reliability by determining its health status after injecting faults. The framework proposed in this paper verifies the availability...
Distribution network in our country mostly uses the neutral point grounding way directly namely the small current grounding system, and the single-phase earth fault of distribution network fault is about 80%. When single-phase earth fault occurs, the system can still run 1 ∼ 2 h. This request in the electric power, as soon as possible accurately find out the fault line and the location, based on traditional...
The presence of open-faults in NoC channels drastically drops packets while routing them causing severe degradation of network performance. Nevertheless, it can still be compensated by utilizing a fault-repairing scheme. This paper shows how the performance of a NoC architecture can be improved through self-repairing of open channels using short-defects. Simulation results reveal that the performance...
A design optimization method based on dependency model is proposed for Built-in test design in Prognostics and Health Management. Firstly, simplify the dependency model, eliminate the redundant test and merge the fuzzy fault model. Secondly identify the minimum test vector matrix to each fault mode. Under the principles of reliability and costs, determine the optimal test vector, which is used as...
Power dissipation is a major issue with testing of designs having full scan architectures. The proposed scan technique minimizes toggle activity while scanning in test patterns. The method uses bit inversion technique to avoid toggles in scan flip-flops. The setup is dynamically configurable to one among the logic reversal structure and traditional scan while shift-in/shift-out of test patterns. Experimental...
The article provides the method of concurrent error detection (CED) system organisation, based on the constant-weight 1/3-code, with outputs of testing logic circuit combined into groups by 3 outputs. The authors provide the calculation formulas of check functions of complements, that allow not only to form the set of testing combinations for «1-out-of-3»-code (1/3-code) checker, but also to form...
Multi-cycle scan-based tests allow more faults to be detected by keeping the circuit in functional mode for more than one clock cycle. Optimizing a multi-cycle test set can improve test quality and/or test application time. It is also possible to capture the primary outputs of a circuit multiple times between the scan operations. This ensures that if a fault is detected at the primary outputs, increasing...
This paper is devoted to the development of objects and methods in on-line testing. Requirements imposed to computer systems and on-line testing of their digital components are analyzed in efficiency of use of resources and in restriction of the hidden processes. The low level of execution of these requirements in the modern computer systems and in circuits of on-line testing because of domination...
Triggered vacuum switch (TVS) has tiny turn-on time, huge power capacity and breaking ability in zero-crossing, and can be used to implement controlled reclosing technology. However, TVS has to break circuit reliably in zero-crossing. The reclosing peak current and transient voltage in 10 kV lines was estimated to determine the electrical transient parameters that the TVS worked with, and then an...
The approach proposed in this paper engages FFT to the linear analog circuit specifications determination. The method allows to calculate the observed circuit under test parameter based on the step response analysis. The approximating equation that models the relationship between the selected frequency components and the observed specification is determined by means of multiple linear regression....
This paper presents a converter topology for the realisation of high power grid simulators. This can be used for highly flexible simulation and testing of the grid compliance of renewable energy conversion systems, even for the certification procedure of the electrical characteristics.
Over the past decades, many synchrophasor applications have been developed but the performance under various PMU errors has not been explored and is unknown for most applications. This paper discusses the impact of PMU measurement errors and limitations originated from hardware implementation of various phasor estimation algorithms on the accuracy of the synchrophasor-based fault location application,...
The need to maintain and replace ageing equipment in South African national energy utility (ESKOM) and local municipalities has increased over the years. The country is currently experiencing power cuts from time to time inconveniencing factories and customers at large, as a result. This paper focuses only on the maintenance planning and execution of protection system of the utility distribution substations...
Spin transfer torque magnetic random access memory (STT-MRAM) is a competitive, future memory technology for last-level embedded caches. It exhibits ultra-high density (3–4X of SRAM), non-volatility, nano-second Read and Write speeds, and process and voltage compatibility with CMOS. As the design and fabrication process mature for the STT-MRAM, there is a need to study the various fault models that...
Over the past few decades, the use of reconfigurable computing for aerospace applications has become increasingly common despite its sensitivity to ionizing radiation. Tools are needed to test and implement fault-mitigation mechanisms to increase the reliability of FPGAs in space. This paper introduces a tool called the JTAG Configuration Manager (JCM) that provides high-speed programmable access...
The memristor was originally defined as one of the fundamental electrical elements which provided the vacant connection between charge and flux. So far, most of the research has concentrated on the unique features of the individual devices. And the overall behavior of the multiple memristive systems has not been fully studied. Especially, the lack of corresponding fault diagnosis method for complex...
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